HYB5117800BSJ-50- Datasheet, PDF (6/23 Pages) Siemens Semiconductor Group – 2M x 8 - Bit Dynamic RAM 2k Refresh

HYB 5(3)117800/BSJ-50/-60
2M × 8 DRAM
AC Characteristics ^{5, 6}
T_A = 0 to 70 °C, V_CC = 5 V ± 10 % / V_CC = 3.3 V ± 0.3 V, t_T = 5 ns
Parameter
Symbol
Limit Values
Unit Note
-50
-60
min. max. min. max.
Common Parameters
Random read or write cycle time
RAS precharge time
RAS pulse width
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
CAS hold time
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
Read Cycle
Access time from RAS
Access time from CAS
Access time from column address
OE access time
Column address to RAS lead time
Read command setup time
Read command hold time
Read command hold time referenced to
RAS
CAS to output in low-Z
Output buffer turn-off delay
Output buffer turn-off delay from OE
t_RC
90 –
110 –
ns
t_RP
30 –
40 –
ns
t_RAS
50 10k 60 10k ns
t_CAS
13 10k 15 10k ns
t_ASR
0
–
0
–
ns
t_RAH
8
–
10 –
ns
t_ASC
0
–
0
–
ns
t_CAH
10 –
15 –
ns
t_RCD
18 37 20 45
t_RAD
13 25 15 30 ns
t_RSH
13
15 –
ns
t_CSH
50
60 –
ns
t_CRP
5
–
5
–
ns
t_T
3
50 3
50 ns ⁷
t_REF
–
32 –
32 ms
t_RAC
t_CAC
t_AA
t_OEA
t_RAL
t_RCS
t_RCH
t_RRH
t_CLZ
t_OFF
t_OEZ
–
50 –
60 ns ^{8, 9}
–
13 –
15 ns ^{8, 9}
–
25 –
30
ns ^{8, 10}
–
13 –
15 ns
25 –
30 –
ns
0
–
0
–
ns
0
–
0
–
ns ¹¹
0
–
0
–
ns ¹¹
0
–
0
–
ns ⁸
0
13 0
15 ns ¹²
0
13 0
15 ns ¹²
Semiconductor Group
6
1998-10-01