HYB39S16400-1 Datasheet, PDF (5/19 Pages) Siemens Semiconductor Group – 16 MBit Synchronous DRAM

HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Signal Pin Description (cont’d)
Pin
V_DD
V_SS
V_DDQ
V_SSQ
Type Signal Polarity Function
Supply –
–
Power and ground for the input buffers and the core logic.
Supply –
–
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
CKE
CKE Buffer
CLK
CLK Buffer
A0
A1
A2
12
A3
A4
A5
A6
A7
12
A8
A9
A10
A11 (BS)
CS
CS Buffer
RAS
RAS Buffer
CAS
CAS Buffer
WE
WE Buffer
Self
Refresh Clock
Row Decoder
Row
Address
Counter
Bank A
Row/Column
Select
11
Predecode A
3 ^Sequential
Control
Bank A
11
Mode Register
3 ^Sequential
Control
Bank B
11
Predecode B
Bank B
Row/Column
Select
2048 x 1024
Memory Bank A
2048
1024
Sense Amplifiers
Column Decoder
and DQ Gate
8
Data Latches
8
8
Data Latches
8
Column Decoder
and DQ Gate
Sense Amplifiers
1024
DQM
DQM Buffer
Row Decoder
Memory Bank B
2048 x 1024
2048
Block Diagram for HYB 39S16400CT (2 banks × 2 M × 4 SDRAM)
4
DQ0
DQ1
DQ2
DQ3
SPB02835
Semiconductor Group
5
1998-10-01