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C515 Datasheet, PDF (44/55 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller
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C515
A/D Converter Characteristics
VCC = 5 V + 10%, – 15%; VSS = 0 V
TA = 0 to 70 °C
TA = – 40 to 85 °C
TA = – 40 to 110 °C
for the SAB-C515-1RM
for the SAF-C515-1RM
for the SAH-C515-1RM
VCC – 0.25 V ≤ VAREF ≤ VCC + 0.25 V ; VSS – 0.2 V ≤ VAGND ≤ Vss + 0.2 V; VIntAREF − VIntAGND ≥ 1 V;
Parameter
Analog input voltage
A/D converter input clock
Sample time
Conversion cycle time
Total unadjusted error
Internal resistance of
reference voltage source
Internal resistance of
analog source
ADC input capacitance
Symbol
VAIN
t IN
tS
tADCC
TUE
RAREF
RASRC
Limit Values
min. max.
VAGND -
0.2
VAREF +
0.2
–
2 x t CLCL
–
16 x tIN
–
80 x tIN
–
±1
–
8 x tIN /500
-1
–
tS / 500 - 1
Unit
V
ns
ns
ns
LSB
kΩ
kΩ
Test Condition
1)
2)
3)
V V = IntAREF AREF = VCC
V V = IntAGND AGND = VSS 4)
tIN in [ns] 5) 6)
tS in [ns] 2) 6)
CAIN
–
45
pF 6)
Notes:
1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in
these cases will be 00H or FFH, respectively.
2) During the sample time the input capacitance CAIN can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS.
After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion
result.
3) This parameter includes the sample time tS and the conversion time tC. The values for the conversion clock
tADC is always 8 x tIN.
4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all
other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.
5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.
6) Not 100% tested, but guaranteed by design characterization.
Semiconductor Group
44
1997-08-01
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