C515 Datasheet, PDF (38/55 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

C515
Fail Save Mechanisms
As a means of graceful recovery from software or hardware upset a watchdog timer is provided in
the C515. lf the software fails to clear the watchdog timer at least every 65532 µs (at 12 MHz clock
rate), an internal hardware reset will be initiated. The software can be designed such that the
watchdog times out if the program does not progress properly. The watchdog will also time out if the
software error was due to hardware-related problems. This prevents the controller from
malfunctioning for longer than 65 ms if a 12-MHz oscillator is used. Figure 17 shows the block
diagram of the watchdog timer unit.
f _OSC
÷ 12
16-Bit Watchdog Timer
Reset
WDT Reset if WDT count is between
FFFC _H - FFFF _H
IP0 ( A9H)
- WDTS - - - - - -
External HW Reset
Control Logic
- WDT -
-
-
-
-
- IEN0 ( A8 _H)
- SWDT -
-
-
-
-
- IEN1 ( B8 _H)
MCB03210
Figure 17
Block Diagram of the Watchdog Timer
The watchdog timer can be started by software (bit SWDT) but it cannot be stopped during active
mode of the C515. lf the software fails to clear the watchdog in time, an internally generated
watchdog reset is entered at the counter state FFFCH and lasts four instruction cycles. This internal
reset differs from an external reset only to the extent that the watchdog timer is not disabled. Bit
WDTS (was set by starting WDT) allows the software to examine from which source the reset was
initiated. lf it is set, the reset was caused by a watchdog timer overflow.
Semiconductor Group
38
1997-08-01