SDA2506-5 Datasheet, PDF (3/10 Pages) Siemens Semiconductor Group – Nonvolatile Memory 1-Kbit E2PROM

SDA 2506-5
Reprogram (see figure 2a, 2b and 3)
A complete reprogramming operation consists of an erase operation followed by a write operation.
During erase, all bits of the selected word are set to a uniform 1 state, and during write, 0 states are
created according to the information in the shift register.
A reprogramming operation is started when, after data entry in chip enable, the control bit CB = "1"
appears in the appropriate cell of the shift register. Whether an erase or a write operation is
performed will depend on the information on data line D during chip enable.
For resetting to the "1" state there must also be a "1" on the data input during the transition of CE
from high to low. If a write operation to the 0 state is to be started however, there must be a 0 on the
data line during chip enable.
Reset
A memory that is not selected is automatically in reset status because of the "1" state of CE. All
flipflops of the process control are reset. The information in the shift register is retained on the other
hand and is not altered until data are shifted. The reset status is also produced by an on-chip circuit
when the memory is powered on.
After chip enable a start pulse is required on clock line Φ to initiate programming. The control
information on data line D must remain stable until the rising edge of the start pulse. The
programming operation begins with the trailing edge of the start pulse and ends with transition of CE
from low to high.
The reprogramming of a word begins with an erase operation. For this the word address is entered
together with control bit CB = "1". The entry of the data word is omitted for an erase. But at this point
the data for a following write operation can be entered. If this is intended, the data D0 through D7
for the write operation are entered before entry of the control word for the erase operation. For the
erase the data line has to be kept high during chip enable, i.e. transition of CE from high to low, and
until the falling edge of the start pulse. An erase operation can be followed immediately by a write
operation without entry of the data and word address. For this the data line is sent low, CE is again
driven from high to low (chip enable) and the start pulse for the write operation is put on clock line
Φ. The data line must be kept low until the falling edge of the start pulse (see figure 3).
Erase and write can also be executed separately. For writing, a 16-bit control word (word address
with control bit CB = "1", data D0-D7) is entered. For erasing, only the word address and CB = "1"
are entered. For the erase operation the data line must be kept high during chip enable and until the
falling edge of the start pulse, and for the write operation it must be kept low (see figure 2a and 2b).
Total Erase
If input TP2 (pin 7) is put on V_CC = 5 V, this activates the mode for total erasure of memory. The word
address 0 and control bit CB = "1" must be entered. The data line has to be kept high during chip
enable (transition of CE from high to low) and until the falling edge of the start pulse. A total erase
operation is ended when CE goes from low to high and by switching input TP2 to 0 V.
Semiconductor Group
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