SDA2506-5 Datasheet, PDF (2/10 Pages) Siemens Semiconductor Group – Nonvolatile Memory 1-Kbit E2PROM

SDA 2506-5
Circuit Description
Data Transfer and Chip Control
Three lines, each with several functions, are necessary for overall data transfer between the control
processor and the E²PROM:
a) Data line D
– bidirectional serial data transfer
– serial entry of address and control bit
– direct control, D = 1 for erase, D = 0 for write
b) Clock line Φ
– shift clock for data, address and control bits
– start readout with transfer of data from memory into shift register or start of data change during
reprogramming
c) Chip-enable line CE
– chip reset and data input (active high)
– chip enable (active low)
Before the chip is enabled, data, address and control information is clocked in on the bidirectional
data bus. These data are retained in the shift register during reprogramming and readout until the
second clock pulse. The following data formats have to be entered:
a) Readout memory, one 8-bit control word consisting of
– seven address bits A0 through A6 (A0 first as LSB)
– one control bit CB = "0" after A6
Reprogram Memory
b) Erase, 8-bit input information consisting of
– seven bits of address information A0 through A6 (A0 first as LSB)
– one bit of control information CB = "1" after A6
c) Write, 16-bit input information consisting of
– eight bits of new memory information D0 through D7 (D0 first as LSB)
– seven bits of address information A0 through A6 (A0 first as LSB after D7)
– one bit of control information CB = "1" after A6
d) Erase and write, 16-bit input information consisting of
– eight bits of new memory information D0 through D7 (D0 first as LSB)
– seven bits of address information A0 through A6 (A0 first as LSB after D7)
– one bit of control information CB = "1" after A6
Read (see figure 1)
After data entry, and with CB = 0, the readout operation of the selected word address is started with
the transition of CE from "1" to "0". The information on the data line during chip enable has no effect.
With the first clock pulse after CE = 0, the data word of the selected memory address is transferred
into the shift register. With the trailing edge of the first clock pulse the data output goes low-
impedance and the first data bit D0 can be read on the data pin. Every further clock pulse shifts
another data bit to the output. The data line goes high-impedance again when CE changes from "0"
to "1".
Semiconductor Group
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