HYB5116400BJ-50- Datasheet, PDF (25/26 Pages) Siemens Semiconductor Group – 4M x 4-Bit Dynamic RAM

HYB 5116400BJ/BT-50/-60/-70
4M x 4-DRAM
Test Mode
As the HYB 5116400BJ/BT is organized internally as 1M x 16-bits, a test mode cycle using 4:1
compression can be used to improve test time. Note that in the 4M x 4 version the test time is
reduced by 1/4 for a N test pattern.
In a test mode “write” the data from each I/O pin is written into four 1M blocks simultaneously (all
“1” s or all “0” s). In test mode “read” each I/O output is used for indicating the test mode result. If
the internal four bits are equal, the I/O would indicate a “1”. If they were not equal, the I/O would
indicate a “0”. The WCBR cycle (WE, CAS before RAS) puts the device into test mode. To exit
from test mode, a “CAS before RAS refresh”, “RAS only refresh” or “Hidden refresh” can be
used.Refresh during test mode operation can be performed by normal read cycles or by WCBR
refresh cycles.
Row addresses A0 through A9 have to kept high to perform a testmode entry cycle. All other
addresses are don’t care.
A0C,A1C
Normal
I/O 1
Test
A0C,A1C
Normal
I/O 2
Test
A0C,A1C
Normal
I/O 3
Test
A0C,A1C
Normal
I/O 4
Test
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
1 M Block
Block Diagram in Test Mode
A0C,A1C
Normal
Test
A0C,A1C
Normal
Test
A0C,A1C
Normal
Test
A0C,A1C
Normal
Test
Vcc
I/O 1
Vss
Vcc
I/O 2
Vss
Vcc
I/O 3
Vss
Vcc
I/O 4
Vss
Semiconductor Group
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