SAB80C517_05 Datasheet, PDF (105/323 Pages) Siemens Semiconductor Group – 8-Bit CMOS Single-Chip Microcontroller

On-Chip Peripheral Components
7.5.4.2 Compare Mode 1
In compare mode 1, the software adaptively determines the transition of the output signal. This
mode can only be selected for compare registers assigned to timer 2. lt is commonly used when
output signals are not related to a constant signal period (as in a standard PWM generation) but
must be controlled very precisely with high resolution and without jitter. In compare mode 1, both
transitions of a signal can be controlled. Compare outputs in this mode can be regarded as high
speed outputs which are independent of the CPU activity.
lf mode 1 is enabled, and the software writes to the appropriate output latch at the port, the new
value will not appear at the output pin until the next compare match occurs. Thus, one can choose
whether the output signal is to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-
level) or should keep its old value at the time the timer 2 count matches the stored compare value.
Figure 7-40 shows a functional diagram of a timer/compare register/port latch configuration in
compare mode 1. In this function, the port latch consists of two separate latches. The upper latch
(which acts as a "shadow latch") can be written under software control, but its value will only be
transferred to the output latch (and thus to the port pin) in response to a compare match.
Note that the double latch structure is transparent as long as the internal compare signal is active.
While the compare signal is active, a write operation to the port will then change both latches. This
may become important when driving timer 2 with a slow external clock. In this case the compare
signal could be active for many machine cycles in which the CPU could unintentionally change the
contents of the port latch. For details see also section 7.5.5.1 "Using Interrupts in Combination with
the Compare Function".
A read-modify-write instruction (see section 7.1) will read the user-controlled "shadow latch" and
write the modified value back to this "shadow-latch". A standard read instruction will - as usual - read
the pin of the corresponding compare output.
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