SAB80C517_05 Datasheet, PDF (103/323 Pages) Siemens Semiconductor Group – 8-Bit CMOS Single-Chip Microcontroller

On-Chip Peripheral Components
7.5.4.1 Compare Mode 0
In mode 0, upon matching the timer and compare register contents, the output signal changes from
low to high. lt goes back to a low level on timer overflow. As long as compare mode 0 is enabled,
the appropriate output pin is controlled by the timer circuit only, and not by the user. Writing to the
port will have no effect. Figure 7-38 shows a functional diagram of a port latch in compare mode 0.
The port latch is directly controlled by the two signals timer overflow and compare. The input line
from the internal bus and the write-to-latch line are disconnected when compare mode 0 is enabled.
Compare mode 0 is ideal for generating pulse width modulated output signals, which in turn can be
used for digital-to-analog conversion via a filter network or by the controlled device itself (e.g. the
inductance of a DC or AC motor). Mode 0 may also be used for providing output clocks with initially
defined period and duty cycle. This is the mode which needs the least CPU time. Once set up, the
output goes on oscillating without any CPU intervention. Figure 7-39 illustrates the function of
compare mode 0.
For some information on how to operate a timer/compare register configuration to generate PWM
signals (e.g. by using a compare interrupt), please refer to chapter 7.5.5 where more details about
the configurations can be found, or to chapter 10 where two application examples are provided.
Figure 7-38
Port Latch in Compare Mode 0
Semiconductor Group
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