LRS1382 Datasheet, PDF (97/114 Pages) Sharp Electrionic Components – STACKED CHIP 32M FLASH AND 8M SRAM

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Table 15. Frequency Configuration Settings
Read Configuration Register
Frequency
Configuration Code
RCR.13 RCR.12 RCR.11
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
Input Clock Frequency
TBD ns
24MHz
36MHz
40MHz
TBD MHz
TBD ns
TBD MHz
TBD MHz
TBD MHz
TBD MHz
4.16.2 Frequency Configuration
The read configuration register bits RCR.13, RCR.12 and
RCR.11 indicates the frequency configuration (see Table
14). The frequency configuration informs the number of
clocks that must elapse after ADV# is driven active (V_IL)
before data will be available. This value is determined by
the input clock frequency. See Table 15 for the specific
input CLK frequency configuration. Figure 14 shows data
output latency from ADV# going V_IL for different
frequency configuration codes.
4.16.3 Data Output Configuration
The data output configuration, shown by RCR.9 (see
Table 14), determines the number of clocks that data will
be held valid. The data hold time for the LH28F320BX/
LH28F640BX series can be set to one clock or two clocks
(see Figure 15).
Figure 15. Output Configuration
Synchronous burst mode will be available for future device.
Appendix to Spec No.: MFM2-J13222 Model No.: LRS1382 March 1, 2001
Rev. 2.20