LRS1329 Datasheet, PDF (6/27 Pages) Sharp Electrionic Components – Stacked Chip 16M Flash and 2M SRAM

SHARI=
LRS1329
4
3. Truth Table (*l)
F-DQ
Flash
SRAM Note F-a F-B F-3 F-E S-CE, S-GE, S-s S* F-mtoDPh , to hu&
H
DOUT
Read
output
*4.5
Standby
LH
L
H
*7
L DOUT 1 High-Z
x x.7-.
Bigh-Z
Disable ’
Write
*2,3,4
H
L
H
DIN
L DIN High-Z
Standby
Read
*6
output
Disable *6
HH ’ ’
LH
L
DOUT
H
H
X High-Z High-Z
Write
*6
L
DIN
Read
*6
Reset Power Output
Down
Disable *6
Write
*6
XLXXLH
L
H
H-
L
DOUT
X High-Z Bigh-2
DIN
Standby ’
*6
HH
Standby -
Reset Power
*6
Down
xL
xx
*7
xx x
High-Z
tes) *l. L=V,,, H=V,, , X=H or L . Refer to DC Characteristics.
*2. Commandwrites involving block erase or word/byte write are reliably executed when
F-V,,+., and F-V,=2.7V to 3-W. Block erase or word/byte write with V,,<F-B<V,
produce spurious results and should not be attempted.
*3. Refer Section 5. Flash Memory Comand Definition for valid
*4. Never hold F-2 low and F-s low at the same timing.
*5. F-A., set to V,, or VI, in byte mode (F-B-YTE=Vn).
-1
*6. F-‘RP set to V,, or V,, .
DIN during
a write
operation.
*7. See the following SRAM Standby mode.
Block Diagram
F-V, F-V,
F-GND
----------------,
.F-?i?
F-X
F-E
F-m
F*
F-BYTE
i =-
:’
+
:>
:T
.
16M(x8/x16) bi t
Flash memory
S-A,,
S-E,
s-c>
S-OE
S-IRE
4b
I>
j>
;>
2M (x8) bit
SRAM
> F-RY/?%
F-D’& to F-W,,
+DQ, to W,
s-v,
S-GND