LRS1329 Datasheet, PDF (26/27 Pages) Sharp Electrionic Components – Stacked Chip 16M Flash and 2M SRAM

SHARF)
LRS1329
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17. Design Considerations
1. Power Supply Decoupling
To avoid a bad effect to the system by flash memory power switching characteristics,
each device should have a O.lpF ceramic capacitor connected between its V, and GND
and between its V,,and CND. Low inductance capacitors should be placed as close as
possible to package leads.
2. V,,Trace on Printed Circuit Boards
Updating the memory contents of flash memories that reside in the target system requires
that the printed circuit board designer pay attention to the Vr, Power Supply trace.
Use similar trace widths and layout considerations given to the Vcc power bus.
3. The Inhibition of Overwrite Operation
Please do not execute reprogramming “0” for’the bit which has already been
programed “0”. Overwrite operation may generate unerasable bit.
In case of reprogramming “0” to the data which has been programed “1”.
* Program “0” for the bit in which you want to change data from “1” to “0”.
* Program “1” for the bit which has already been programmed “0”.
For example, changing data from “1011110110111101” to “1010110110111100” requires
“1110111111111110” programming.
4. Power Supply
Block erase, full chip erase, word/byte write and lock-bit configuration with an invalid
V,,(See 11. DC Characteristics) produce spurious results and should not be attempted.
Device operations at invalid Vcc voltage(see ll.DC Characteristics)
results and should not be attempted.
produce spurious
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