LRS1302 Datasheet, PDF (4/61 Pages) Sharp Electrionic Components – Stacked Chip 8M Flash and 1M SRAM

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SHARP
LRS13023
2
Part 1 Overview
l.Description
The LRS1302 is a combination memory organized as 1,048,576X 8
memory and _131,072X8 bit static RAM in one package.
It is fabricated using silicon-gate CMOS process technology.
bit flash
OAccess Time
Flashmemoryaccesstime
SRAM access time
OOpemtingcment
Flash memory Read
Byte write
Block erase
SRAM
Operating
ostandbycurrent
Flash memory
-***
. ...
. ...
....
....
- -**
.. ..
130 nsMax.
70 nsMax.
12 mAMax.
57 mAMax.
37 mAMax.
25 mAMax.
,
(t&ti2Oons>
hcxJ&oons)
20 pA Max. (F-EZF-Vc,0.2V,
EbO.2V, F-V&O.2V)
Sk4M
. .. .
30 @ Max. (S-=ZS-Vc,0.2V)
.. ..
0.7 @ Typ. (T,=25”c, S-V,-3V,
s-CEZS-vcc-0.2v)
(Total standby current is the summation of Flash memory’s standby current and SRAM’s one.)
3Power supply
.. ..
2.7V to 3.6V @ead/SPAM write)
2.7~ to 3.6~ (FLASH erase/write>Cr,=O to 85c
3SRAM data retention voltage
3Operating temperature
.. ..
IFully static operation
3Three-state output
JNot designed or rated as radiation hardened
2.0 V Min.
40°C to +85”c
240 Pin TSOP ( TSOP~O-p-0819 plastic package
IFlash memory has P-type bulk silicon, and SRAM has N-type bulk silicon.
The contents described in Part 1 take first priority over Part 2 and Part 3.