LRS1302 Datasheet, PDF (35/61 Pages) Sharp Electrionic Components – Stacked Chip 8M Flash and 1M SRAM

SHARI=
LRS13023
33
DC Characteristics (Continued)
VoH2 Output High Voltage
6
0.85
V v,-=v,,Min
cMos)
V,,
&=-2.5uA
Vcc
V
-0.4
VP,, V,, Lockout during
3,6
Normal Operations
1.5
V
V,, VP, during Byte Write,
2.7
3.6
V TA=O to 85°C
Block Erase or Lock-Bit
Operations
V, .KO V,, Lockout Voltage
2.0
V
VI-II-I ^{Rp Unlock Voltage}
7,;
11.4
12.6
V Set master lock-bit
Override master and block lock-bit
NOTES:
1. All currents are in RMS unless otherwise noted.
2. kcws~dhEs
are specified with the device de-selected. If read or byte written while in erase suspend mode,
the device’s current draw is the sum of kms or kcEs and &-- or &--JJ, respectively.
3. Block erases, byte writes, and lock-bit configurations are inhibited when VPPIvPPx, and not guaranteed in the
range between VPPx(Max> and VP&&n) and above VP&Max).
4. Automatic Power Savings @F’S) reduces typical ~C-J to 3mA at 3.3V V,- in static operation.
5. CMOS inputs are either V,-c-+0.2V or GNDk0.2V. TTL inputs are either V, or V,.
..
6. Sampled, not 100% tested.
7. Master lock-bit set operations are inhibited when D=V,,. Block lock-bit configuration operations are inhibited
when the master lock-bit is set and Rp=V,. Block erases and byte writes are inhibited when the corresponding
block-lock bit is set and P=VIH.
8. m connection to a V, supp 1y is allowed for a Maximum cumulative period of 80 hours.