LH28F160SGED-L10 Datasheet, PDF (4/42 Pages) Sharp Electrionic Components – 16 M-bit (512 kB x 16 x 2-Bank) SmartVoltage Dual Work Flash Memory

LH28F160SGED-L10
PIN DESCRIPTION
SYMBOL
TYPE
A0-A18
INPUT
DQ0-DQ15
INPUT/
OUTPUT
BE0#,
BE1#
INPUT
RP#
INPUT
OE#
WE#
WP#
INPUT
INPUT
INPUT
VPP
SUPPLY
VCC
SUPPLY
GND
NC
SUPPLY
NAME AND FUNCTION
ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
data during memory array, status register, and identifier code read cycles. Data pins
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
BANK ENABLE : Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. When BE0# are "low", bank0 is in active. When BE1# are "low", bank1
is in active. Both BE0# and BE1# must not be low at the same time. BE0#, BE1#-high
deselects the device and reduces power consumption to standby levels.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
RP# at VHH allows to set permanent lock-bit. Block erase, word write, or lock-bit
configuration with VIH ≤ RP# ≤ VHH produce spurious results and should not be
attempted.
OUTPUT ENABLE : Controls the device's outputs during a read cycle.
WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
WRITE PROTECT : Master control for block locking. When VIL, locked blocks cannot be
erased and programmed, and block lock-bits cannot be set and reset.
BLOCK ERASE, WORD WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY :
For erasing array blocks, writing words, or configuring lock-bits. With VPP ≤ VPPLK,
memory contents cannot be altered. Block erase, word write, and lock-bit configuration
with an invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious
results and should not be attempted.
DEVICE POWER SUPPLY : Internal detection configured the device for 2.7 V, 3.3 V or
5 V operation. To switch from one voltage to another, ramp VCC down to GND and then
ramp VCC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write
attempts to the flash memory are inhibited. Device operations at invalid VCC voltage
(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should
not be attempted.
GROUND : Do not float any ground pins.
NO CONNECT : Lead is not internal connected; recommend to be floated.
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