LRS1331 Datasheet, PDF(22/26 Page) Sharp Electrionic Components – Stacked Chip 16M Flash Memory and 4M SRAM

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LRS1331 Datasheet, PDF (22/26 Pages) Sharp Electrionic Components – Stacked Chip 16M Flash Memory and 4M SRAM

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LRS1331

Stacked Chip (16M Flash & 4M SRAM)

tWC

ADDRESS

tAW

S-OE

S-CE1

S-CE2

S-UB, S-LB

S-WE

DOUT

tCW

(NOTE 2)

tAS

(NOTE 4)

tBW

(NOTE 3)

tWP

(NOTE 1)

tWR

(NOTE 5)

tWR

(NOTE 5)

HIGH IMPEDANCE

tDW

tDH

DIN

Data Valid

NOTES:

1. A write occurs during the overlap of a LOW S-CE1, a HIGH S-CE2 and a LOW S-WE,

A write begins at the latest transition among S-CE1 going LOW, S-CE2 going HIGH

and S-WE going LOW. A write ends at the earliest transition among S-CE1 going HIGH,

S-CE2 going LOW and S-WE going HIGH. tWP is measured from the beginning of

write to the end of write.

2. tCW is measured from the later of S-CE1 going LOW or S-CE2 going HIGH to the end

of write.

3. tBW is measured from the time of going LOW S-UB or LOW S-LB to the end of write.

4. tAS is measured from the address valid to the beginning of write.

5. tWR is measured from the end of write to the address change. tWR applied in case a write ends

as S-CE1 going HIGH, S-CE2 going LOW or S-WE going HIGH.

Figure 11. Write Cycle Timing Diagram (S-UB, S-LB Control)

1331-11

Data Sheet

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