LRS1331 Datasheet, PDF (1/26 Pages) Sharp Electrionic Components – Stacked Chip 16M Flash Memory and 4M SRAM

Data Sheet
LRS1331
Stacked Chip
16M Flash Memory and 4M SRAM
FEATURES
• Flash Memory and SRAM
• Stacked Die Chip Scale Package
• 72-ball 8 mm × 11 mm CSP plastic package
• Power supply: 2.7 V to 3.6 V
• Operating temperature: -25°C to +85°C
• Flash Memory
– Access time (MAX.): 90 ns
– Operating current (MAX.)
(The current for F-V_CC pin and F-V_CCW pin):
– Read: 25 mA (t_CYCLE = 200 ns)
– Word write: 57 mA
– Block erase: 42 mA
– Standby current (the current for F-V_CC pin): 15 µA
(MAX. F-RP ≤ GND ± 0.2 V)
– Optimized array blocking architecture
– Two 4K-word boot blocks
– Six 4K-word parameter blocks
PIN CONFIGURATION
72-BALL FBGA
INDEX
– Thirty-one 32K-word main blocks
– Bottom boot location
– Extended cycling capability
– 100,000 block erase cycles
– Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
• SRAM
– Access time (MAX.): 85 ns
– Operating current: 45 mA (MAX.)
– Standby current: 15 µA (MAX.)
– Data retention current: 2 µA (MAX.)
DESCRIPTION
The LRS1331 is a combination memory organized as
1,048,576 × 16-bit flash memory and 262,144 × 16-bit
static RAM in one package.
TOP VIEW
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9 10 11 12
A NC NC NC A₁₁ A₁₅ A₁₄ A₁₃ A₁₂ F-GND NC NC NC
B
A₁₆ A₈ A₁₀ A₉ DQ₁₅ S-WE DQ₁₄ DQ₇
C
F-WE ^F-RY/
BY
T₁
S-A₁₇ DQ₁₃ DQ₆ DQ₄ DQ₅
D
GND F-RP T₂ T₄ DQ₁₂ S-CE₂ S-V_CC F-V_CC
E
F-WP F-V_PP F-A₁₉ DQ₁₁ T₃ DQ₁₀ DQ₂ DQ₃
F
S-LB S-UB S-OE NC DQ₉ DQ₈ DQ₀ DQ₁
G
F-A₁₈ F-A₁₇ A₇ A₆ A₃ A₂ A₁ S-CE₁
H NC NC NC A₅ A₄ A₀ F-CE F-GND F-OE NC NC NC
NOTE: All F-GND and S-GND pins are connected on the board.
Two NC pins at the corner are connected.
Figure 1. LRS1331 Pin Configuration
LRS1331-1
Data Sheet
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