GS2960A Datasheet, PDF (94/99 Pages) Gennum Corporation – Ancillary data extraction

5. Application Reference Design
5.1 Typical Application Circuit
+3.3V
Power Filtering
EQ_VCC +1.2V
0R
0R
10n
1u
1u
10n
10n
1u
+1.2V_A
1u
10n
Power Decoupling
+1.2V
+1.2V_A
10n
10n
10n
10n
10n
10n
10n
0R
10n
1u
A_GND
CD_VDD
1u
10n
IO_VDD
A_GND
1u
IO_VDD
A_GND
+3.3V_A
10n
10n
10n
10n
10n
10n
10n
0R
10n
1u
0R
A_GND
+3.3V_A
1u
10n
A_GND
Place close to GS2960A
A_GND
Place close to GS2960A
+1.2V_A
R7
105R
C18
33u
SMPTE_BY PASS
DVB_ASI
TIM_861
SW_EN
IOPROC_EN/DIS
20BIT/10BIT
RC_BY P
JTAG/HOST
STANDBY
RESET
SDO_EN/DIS
SDOUT_TDO
SDIN_TDI
SCLK_TCK
CS_TMS
EQ_VCC
Place close to GS2960A
A_GND
+1.2V_A
+3.3V_A
+1.2V IO_VDD
DNP
1u
47n
DNP
+3.3V_A
R19
DNP
A3 _{LB_CONT}
A1 _VBG
A2 _LF
B3 _RSV
A_GND
TP
16p
H6 _{XTAL_OUT}
J6 _XTAL2
16p CS10-27.000M
K6 _XTAL1
CD_DISABLEb
G7 _{SMPTE_BY PASS}
G8
H5
D7
H8
H7
DVB_ASI
TIM_861
SW_EN
IOPROC_EN/DIS
20BIT/10BIT
G3
D8
K2
RC_BY P
JTAG/HOST
STANDBY
C7
J2
RESET_TRST
SDO_EN/DIS
H3 _RSV
GS2960AIBE3
STAT2
STAT1
STAT0
B5
A6
A5
22R
22R
22R
PCLK ^A8
22R
DOUT 19 ^B8
22R
DOUT 18 ^A9
22R
DOUT 17 ^A10
22R
DOUT 16 ^B9
22R
DOUT 15 ^B10
22R
DOUT 14 ^C9
22R
DOUT 13 ^C10
22R
DOUT 12 ^C8
22R
DOUT 11 ^E10
22R
DOUT 10 ^E9
22R
DOUT 9 ^F10
22R
DOUT 8 ^F9
22R
DOUT 7 ^H10
22R
DOUT 6 ^H9
22R
DOUT 5 ^J10
22R
DOUT 4 ^J9
22R
DOUT 3 ^K10
22R
DOUT 2 ^K9
22R
DOUT 1 ^J8
22R
DOUT 0 ^K8
22R
STAT3 ^B6
STAT4 ^C5
STAT5 ^C6
E7
E8
F8
F7
SDOUT_TDO
SDIN_TDI
SCLK_TCK
CS_TMS
K4
J4
H4
J3
K3
EQ_VCC
F2
G1
G2
RSV
RSV
RSV
J5
K5
DOUT[19:0]
F/DE (DEFAULT, PROGRAMMABLE)
V/VSY NC (DEFAULT, PROGRAMMABLE)
H/HSY NC (DEFAULT, PROGRAMMABLE)
PCLK
DOUT[19:0]
LOCKED (DEFAULT, PROGRAMMABLE)
Y /1ANC (DEFAULT, PROGRAMMABLE)
DATA_ERRORb (DEFAULT, PROGRAMMABLE)
10n
10n
UCBBJE20-1
1
A_GND
6n2
75R
75R
A_GND
1u
1 _VEE
VEE ¹²
2 _{SDIN GS2974BCNE3 SDO} 11
3 _SDIN
SDO ¹⁰
1u
4 _VEE
VEE ⁹
37R4
A_GND
A_GND
A_GND
470n
A_GND
10n
470n
A_GND
A_GND
C1 _SDI
D1 _SDI
F1 _TERM
Close to
pin C1 &
10n
D1 of
GS2960A
A_GND
A_GND
SDO
SDO
K1
J1 ^A_GND
Close to
pin 1 & 2
of GS2978
10n
49R9
1 _SDI
SDO ¹²
49R9
2 _{SDI GS2978-CNE3 SDO} 11
3 _VEE
SD/HD ¹⁰
4
A_GND
RSET
VCC ⁹
750R
CD_VDD
CD_DISABLEb
10n
A_GND
75-ohm Traces
4u7
75R
75R ^CD_VDD
A_GND
10n
75R
5n6
A_GND
UCBBJE20-1
1
4u7
75R
CD SLEW RATE SELECT
CD_VDD
A_GND
Notes:
1. The value of the series resistors on video data, clock, and timing
connections should be determined by board signal integrity test.
2. For analog pow er and ground isolation refer to PCB layout guide.
3. For critital 3G signal layout refer to PCB layout guide.
4. For impedance controlled signal layout refer to PCB layout guide.
GS2960A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54384 - 2
September 2012
94 of 99