GS2960A Datasheet, PDF (92/99 Pages) Gennum Corporation – Ancillary data extraction

4.21 JTAG Test Operation
When the JTAG/HOST pin of the GS2960A is set HIGH and the SMPTE_BYPASS pin is
LOW, the host interface port is configured for JTAG test operation. In this mode, pins E7,
F8, F7, and E8 become TDO, TCK, TMS, and TDI. In addition, the RESET_TRST pin
operates as the test reset pin.
Boundary scan testing using the JTAG interface is enabled in this mode.
There are two ways in which JTAG can be used:
1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test
Equipment) during PCB assembly.
2. Under control of a host processor for applications such as system power on self
tests.
When the JTAG tests are applied by ATE, care must be taken to disable any other devices
driving the digital I/O pins. If the tests are to be applied only at ATE, this can be
accomplished with tri-state buffers used in conjunction with the JTAG/HOST input
signal. This is shown in Figure 4-41.
Application HOST
GS2960A
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_HOST
Figure 4-41: In-Circuit JTAG
In-circuit ATE probe
Alternatively, if the test capabilities are to be used in the system, the host processor may
still control the JTAG/HOST input signal, but some means for tri-stating the host must
exist in order to use the interface at ATE. This is represented in Figure 4-42.
Application HOST
GS2960A
CS_TMS
SCLK_TCK
SDIN_TDI
Tri-State
In-circuit ATE probe
Figure 4-42: System JTAG
SDOUT_TDO
JTAG_HOST
GS2960A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54384 - 2
September 2012
92 of 99