SH3002 Datasheet, PDF (8/22 Pages) Semtech Corporation – Reset Management and Clock Management Support IC for Microcontrollers

SH3002 MicroBuddy™
SYSTEM MANAGEMENT
The SH3002 employs a Frequency Locked Loop
(FLL) to synchronize the HF clock to the 32.768 kHz
reference. This architecture has several advantages
over the common PLL (Phase Locked Loop) systems,
including the ability to stop and re-start without
frequency transients or instability, and with instant
settling to a correct frequency. The conventional PLL
approach invariably includes a Low-Pass Filter that
requires a long settling time on re-start.
The primary purpose of the FLL is the maintenance
of the correct frequency while the ambient temperature
is changing. As the temperature drift of the HF oscillator
is quite small, any corrective action from the FLL system
is also small and gradual, commensurate with the
temperature variation.
The FLL system in the SH3002 is unconditionally
stable.
To set a new frequency for the FLL, the host
Table 2. EMI reduction with Spectrum Spreading
Setting
Spreading Peak EMI Peak EMI
Bandwidth Reduction Reduction
(guaranteed) (measured)
En CFG1 CFG0 ^kHz
db
db
0X
X
Off
0
0
10
0
32
-3
-3
10
1
64
-6
-7
11
0
128
-9
-10
11
1
256
-12
-15
processor writes the 13-bit Frequency Set value. The
resulting output frequency is calculated using simple
formulas [1] and [2] (reference frequency is 32.768 kHz):
FOSC = 2048 Hz * (Frequency Set value + 1) [1]
FOUT = FOSC / (Post-divider setting) [2]
For example, a post-divider setting of ÷8 and the
Frequency Set value of 4000 (0x0FA0) produce an
output frequency of 1.024 MHz.
Programmable Spectrum Spreading
Most commercial electronic systems must pass
regulatory tests in order to determine the degree of their
Electromagnetic Interference (EMI) affecting other
electronic devices. In some cases compliance with the
EMI standards is costly and complicated.
The SH3002 offers a technique for reducing the
EMI. It can be a part of the initial design strategy, or it
can be applied in the prototype stage to fix problems
identified during compliance testing. This feature of the
SH3002 can greatly reduce the requirements for
radiofrequency shielding, and permits the use of simple
plastic casings in place of expensive RFI-coated or
metal casings.
The SH3002 employs Programmable Spectrum
Spreading in order to reduce the RF emissions from the
processor’s clock. There are five (5) possible settings;
please see Table 2 for operating and performance
figures in the 8-16 MHz range.
Spectrum Spreading is created by varying the
frequency of the HF oscillator with a pseudo-random
sequence (with a zero-average DC component). The
Maximum-Length Sequence (MLS) 8-bit random number
generator, clocked by 32.768 kHz, is used. Only 4, 5, 6,
or 7 bits of the generated 8-bit random number are used,
according to the configuration setting.
Maximum fluctuations of the frequency depend on
the selected frequency range and the position within the
range. Selecting the HF oscillator frequency to be near
the high end of the range limits the peak variations to
± 0.1%, ± 0.2%, ± 0.4%, or ± 0.8% (corresponding to the
configuration setting).
Special Operating Modes
The SH3002 can operate stand-alone, without
connections to the In and Out terminals of the host’s
oscillator. For example, a bank of SH3002 chips can
generate several different frequencies for simultaneous
use in the system, all controlled by a single micro (and
possibly sharing one 32.768 kHz crystal by chaining the
CLK32 pin to XIN pin on the next device). In this case
the CLKIN pin should be connected to VSS. The clock
output on the CLKOUT pin is continuous; the correct
operating mode is automatically recognized by the
SH3002.
A microcontroller might not have a STOP command.
With the SH3002, this controller can do a “simulated”
STOP by issuing an instruction to the SH3002 to stop
the clock. This command is accepted only if the Periodic
Interrupt / Wakeup Timer has started (otherwise, once
the system is put to sleep, it would never wake up
again). This mode of operations is only possible if the
host processor is capable of correct operations with
clock frequency down to zero, and keeps all of the
internal RAM alive while the clock is stopped.
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