SH3002 Datasheet, PDF (7/22 Pages) Semtech Corporation – Reset Management and Clock Management Support IC for Microcontrollers

SH3002 MicroBuddy™
SYSTEM MANAGEMENT
Clock Management System
The SH3002 provides a flexible tool for creating and
managing clocks, a versatile and accurate “any
frequency” clock synthesizer (see Figure 4).
It is capable of generating any frequency in the
range of 62.5 kHz to 16.0 MHz, with worst-case
resolution of 0.0256% (256 ppm). The internal
32.768 kHz clock can also be routed to the CLKOUT pin
(and HF oscillator stopped for energy savings).
The objectives, features, and behavior of the Clock
Management System are aimed towards the systems
that utilize a microcontroller, a microprocessor, a DSP or
an ASIC.
The SH3002 permits the automatic sensing of the
intentions of the host processor, an industry first. The
SH3002 shuts down its clock output when it senses that
the host processor issued a STOP instruction.
Subsequently, the SH3002 idles, consuming less than
10 µA. As soon as the host exits the STOP mode, the
SH3002 instantaneously starts to supply a stable clock
(<2 µs wake-up).
A typical system, constructed with a ceramic
resonator or a crystal as the frequency determining
element, must wait at least several hundred
microseconds (for a resonator), or as much as 100 ms or
more (for a HF crystal), to re-start the oscillator. The
SH3002 allows the response to and service of an event
to finish with a speed previously unattainable for a
simple microprocessor. A system with a traditional clock
approach can be as much as 100x – 10,000x slower.
Clock Generator Operation
The frequency synthesizer in the SH3002 is
constructed from the 2:1 tunable 8.0–16.0 MHz HF
oscillator followed by a programmable “power-of-two”
post-divider (see Figure 4).
The Clock Source selector and the programmable
post-scale divider allow instantaneous switching
between the 32.768 kHz internal clock and divided-down
HF oscillator output. There is no settling or instability
when the switch occurs.
This is a preferred method for clock control in
computing systems, when the large ratio between high
and low frequency of operations allows for
correspondingly large and instantaneous savings in
power consumption.
When the HF oscillator is operating alone, it can set
the frequency of the clock on the CLKOUT pin to
± 0.025%, and maintain it to ± 0.5% over temperature.
This compares favorable with the typical ± 0.5% initial
clock accuracy and ± 0.6% overall temperature stability
of ceramic resonators. The SH3002 replaces the typical
resonator, using less space and providing better
performance and functionality.
The HF oscillator can also be locked to the internal
32.768 kHz signal. The absolute accuracy and stability
of the HF clock depends on the quality of the 32.768 kHz
internally generated clock; the low-frequency (LF)
Oscillator System is described later in this document.
32.768 kHz
FLL On
Frequency Locked Loop
÷ ^{2048 Hz}
16
Logic
Clock Source
Clock On
1
Post-scaler
0
(Divide by 1, 2, 4,
8, 16, 32, 64, 128)
18-bit
DCO Code
Register
CLKOUT
Clock Buffer
and Glue
Logic
16
CLKIN
15
START/STOP
HF Digitally
Controlled
Oscillator
8-16 MHz
Force
DCO On
From / To
Serial I/O
13-bit
Frequency
Set value
8-bit Pseudo
Random Noise
Generator
Figure 4. Simplified HF Oscillator System
Spectrum
Spreading
Controls
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