SH3002 Datasheet, PDF (6/22 Pages) Semtech Corporation – Reset Management and Clock Management Support IC for Microcontrollers

SYSTEM MANAGEMENT
Since the clock is only active for the last 1 or 2 ms of
the reset interval, when VDD has already been valid for
some time, energy savings are realized and the startup
of the whole system is made easier. The commonly
used reset approach forces the processor to turn the
oscillator on and to run at full speed (thus consuming full
power) during the critical time when the (possibly
depleted) battery is trying to raise VDD to an acceptable
level. In contrast, the SH3002 allows the power source
to charge the bypass capacitors and raise the level of
VDD with little additional load. Only when power has
stabilized is the target micro permitted to start expending
energy.
When a brownout event occurs, the SH3002
continues to provide the clock to the target processor,
but at a reduced frequency between 500 kHz and
1.0 MHz. After a delay of 2 ms this clock is stopped,
automatically lowering the energy consumption of the
whole system, see Figure 2.
A Noise Filter (see Figure 1) prevents reset
activations from noise and small power glitches on the
VDD line. A typical behavior is shown in Figure 3 for the
VDD level just above VBO and various amplitudes and
durations of the negative-going spikes.
When VDD is falling, both reset lines are guaranteed
to activate within 5 µs from the time VBO is crossed over.
SH3002 MicroBuddy™
VBO + VHYST
VBO
VDD _1V
3-5ms
RST
12ms minimum
6ms
NRST
CLKOUT
Undefined
1 ms
Normal
FOUT
2 ms
2 ms
Reduced FOUT
0.5-1.0 MHz
Figure 2. Operations of low VDD / Brownout Detector
10
Duration
5
Guaranteed reset
Guaranteed NO reset
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Am plitude, V
Figure 3. Response to negative voltage spikes
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