GS2971 Datasheet, PDF (75/148 Pages) Semtech Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Audio and Video Processing

In SD mode, ancillary data is placed in the LSW of the FIFO. The MSW is set to zero.
If the ANC_TYPE registers are all set to zero, the device extracts all types of ancillary
data. If programmable ancillary data extraction is required, then up to five types of
ancillary data to be extracted can be programmed in the ANC_TYPE registers (see
Section 4.17.1).
Additionally, the lines from which the packets are to be extracted can be programmed
into the ANC_LINEA[10:0] and ANC_LINEB[10:0] registers, allowing ancillary data from
a maximum of two lines per frame to be extracted. If only one line number register is
programmed (with the other set to zero), ancillary data packets are extracted from one
line per frame only. When both registers are set to zero, the device extracts packets from
all lines.
To start Ancillary Data Extraction, the ANC_DATA_EXT_MASK bit of the host interface
must be set LOW. Ancillary data packet extraction begins in the following frame (see
Figure 4-30: Ancillary Data Extraction - Step A).
Application Layer
Read Pointer
Internal Write
Pointer
Bank A
0 ANCDATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
800h
Bank B
0
800h
1023
BFFh
1023
BFFh
ANC_DATA_SWITCH = LOW
Figure 4-30: Ancillary Data Extraction - Step A
Ancillary data is written into Bank A until full. The Y/1ANC and C/2ANC output flags
can be used to determine the length of the ancillary data extracted and when to begin
reading the extracted data from memory.
While the ANC_DATA_EXT_MASK bit is set LOW, the ANC_DATA_SWITCH bit can be
set HIGH during or after reading the extracted data. New data is then written into Bank
B (up to 1024 x 16-bit words), using the corresponding host interface addresses (see
Figure 4-31: Ancillary Data Extraction - Step B).
GS2971 3Gb/s, HD, SD SDI Receiver
Data Sheet
45898 - 2
September 2012
75 of 148