TS51221 Datasheet, PDF (7/18 Pages) Semtech Corporation – High Efficiency Regulator IC for Wireless Power Receiver Applications

Functional Description
The TS51221 wireless power receiver device is a switching
converter that includes flexibility to be used for a wide range
of input voltages and is optimized for high efficiency power
conversion with low R_DSON integrated synchronous switches. A
1MHz internal switching frequency facilitates low cost LC filter
combinations.Additionally, the fixed output versions enable
a minimum external component count to provide a complete
regulation solution with only 4 external components: an input
bypass capacitor, an inductor, an output capacitor, and the
bootstrap capacitor.
VOUT = 0.9 (1 + RTOP/RBOT)
The input to the FB pin is high impedance, and input current
should be less than 100nA.As a result, good layout practices
are required for the feedback resistors and feedback traces.
When using the adjustable version, the feedback trace should
be kept as short as possible and minimum width to reduce
stray capacitance and to reduce the injection of noise.
For the adjustable version, the ratio of VCC/VOUT cannot exceed
16.
Detailed Pin Descripttion
Unregulated input, VCC
This terminal is the unregulated input voltage source from
the rectified receiver coil voltage.It is recommended that a
10uF bypass capacitor be placed close to the device for best
performance.Since this is also the main supply for the IC,
good layout practices need to be followed for this connection.
Switching output, VSW
This is the switching node of the regulator.It should be
connected directly to the 4.7uH inductor with a wide, short
trace and to one end of the Bootstrap capacitor.It is switching
between VCC and PGND at the switching frequency.
Ground, GND
This ground is used for the majority of the device including the
analog reference, control loop, and other circuits.
Bootstrap control, BST
This terminal will provide the bootstrap voltage required for
the upper internal NMOS switch of the buck regulator. An
external ceramic capacitor placed between the BST input
terminal and the VSW pin will provide the necessary voltage
for the upper switch. In normal operation the capacitor is
re-charged on every low side synchronous switching action.
In the case of where the switch mode approaches 100% duty
cycle for the high side FET, the device will automatically reduce
the duty cycle switch to a minimum off time on every 8th cycle
to allow this capacitor to re-charge.
Sense feedback, FB
This is the input terminal for the output voltage feedback.
For the fixed mode versions, this should be hooked directly
to V_OUT.The connection on the PCB should be kept as short
as possible, and should be made as close as possible to the
capacitor.The trace should not be shared with any other
connection. (Figure 23)
For adjustable mode versions, this should be connected to
the external resistor divider. To choose the resistors, use the
following equation:
Power Ground, PGND
This is a separate ground connection used for the low side
synchronous switch to isolate switching noise from the rest of
the device.(Figure 23)
Enable, high-voltage, EN
This is the input terminal to activate the regulator.The input
threshold is TTL/CMOS compatible. It also has an internal pull-
up to ensure a stable state if the pin is disconnected.
Power Good Output, PG
This is an open drain, active low output.The switched mode
output voltage is monitored and the PG line will remain low
until the output voltage reaches the VOUT -UV threshold. Once
the internal comparator detects the output voltage is above
the desired threshold, an internal delay timer is activated and
the PG line is de-asserted to high once this delay timer expires.
In the event the output voltage decreases below VOUT -UV, the
PG line will be asserted low and remain low until the output
rises above VOUT -UV and the delay timer times out.See Figure 2
for the circuit schematic for the PG signal.
TS51221
Final Datasheet
April 6, 2015
Rev 1.1
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