TS51221 Datasheet, PDF (14/18 Pages) Semtech Corporation – High Efficiency Regulator IC for Wireless Power Receiver Applications

External Component Selection
The 1MHz internal switching frequency of the TS51221
facilitates low cost LC filter combinations. Additionally, the
fixed output versions enable a minimum external component
count to provide a complete regulation solution with only 4
external components: an input bypass capacitor, an inductor,
an output capacitor, and the bootstrap capacitor. The internal
compensation is optimized for a 44uF output capacitor and a
4.7uH inductor.
For best performance, a low ESR ceramic capacitor should be
used for CBYPASS.If CBYPASS is not a low ESR ceramic capacitor, a
0.1uF ceramic capacitor should be added in parallel to CBYPASS.
The minimum allowable value for the output capacitor is
33uF. To keep the output ripple low, a low ESR (less than
35mOhm) ceramic is recommended. Multiple capacitors can
be paralleled to reduce the ESR.
The inductor range is 4.7uH +/-20%.For optimal over-current
protection, the inductor should be able to handle up to the
regulator current limit without saturation. Otherwise, an
inductor with a saturation current rating higher than the
maximum IOUT load requirement plus the inductor current
ripple should be used.
For high current modes, the optional Schottky diode will
improve the overall efficiency and reduce the heat. It is up
to the user to determine the cost/benefit of adding this
additional component in the user’s application.The diode is
typically not needed.
For the adjustable output version of the TS51221, the output
voltage can be adjusted by sizing RTOP and RBOT feedback
resistors.The equation for the output voltage is
Vout =

0.9
⋅
¹
+


R_TOP
R_BOT




Thermal Information
TS51221 is designed for a maximum operating junction
temperature TJ of 125°C. The maximum output power is
limited by the power losses that can be dissipated over
the thermal resistance given by the package and the PCB
structures. The PCB must provide heat sinking to keep the
TS51221 cool. The exposed metal on the bottom of the QFN
package must be soldered to a ground plane. This ground
should be tied to other copper layers below with thermal vias.
Adding more copper to the top and the bottom layers and
tying this copper to the internal planes with vias can reduce
thermal resistance further. For a hi-K JEDEC board and 13.5
square inch of 1 oz Cu, the thermal resistance from junction
to ambient can be reduced to Θ_JA = 38°C/W.The power
dissipation of other power components (catch diode, inductor)
cause additional copper heating and can further increase what
the TS51221 sees as ambient temperature.
For the adjustable version, the ratio of VCC/VOUT cannot
exceed 16.
RPUP is only required when the Power Good signal (PG) is
utilized.
TS51221
Final Datasheet
April 6, 2015
Rev 1.1
www.semtech.com
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