TS51221 Datasheet, PDF (12/18 Pages) Semtech Corporation – High Efficiency Regulator IC for Wireless Power Receiver Applications

Typical Application Schematic
Figure 1: TS51221 Application Schematic
PCB Layout
PGND pins. The trace area and length of the switching nodes
VSW and BST should be minimized.
For proper operation and minimum EMI, care must be taken
during PCB layout. An improper layout can lead to issues such
as poor stability and regulation, noise sensitivity and increased
EMI radiation. (figure 23)The main guidelines are the following:
• provide low inductive and resistive paths for loops with
high di/dt,
• provide low capacitive paths with respect to all the other
nodes for traces with high di/dt,
• sensitive nodes not assigned to power transmission should
be referenced to the analog signal ground (GND) and be
always separated from the power ground (PGND).
The negative ends of CBYPASS, COUT and the Schottky diode
DCATCH (optional) should be placed close to each other and
connected using a wide trace. Vias must be used to connect
the PGND node to the ground plane. The PGND node must be
placed as close as possible to the TS51221 PGND pins to avoid
additional voltage drop in traces.
For the adjustable output voltage version of the TS51221,
feedback resistors RBOT and RTOP are required for Vout settings
greater than 0.9V and should be placed close to the TS51221
in order to keep the traces of the sensitive node FB as short
as possible and away from switching signals. RBOT should be
connected to the analog ground pin (GND) directly and should
never be connected to the ground plane. The analog ground
trace (GND) should be connected in only one point to the
power ground (PGND). A good connection point is under the
TS51221 package to the exposed thermal pad and vias which
are connected to PGND. RBOT will be connected to the VOUT
node using a trace that ends close to the actual load.
For fixed output voltage versions of the TS51221, RBOT and RTOP
are not required and the FB pin should be connected directly to
the VOUT.
The bypass capacitor CBYPASS (optionally paralleled to a 0.1µF
capacitor) must be placed close to the VCC pins of TS51221.
The inductor must be placed close to the VSW pins and
connected directly to COUT in order to minimize the area
between the VSW pin, the inductor, the COUT capacitor and the
The exposed thermal pad must be soldered to the PCB for
mechanical reliability and to achieve good power dissipation.
Vias must be placed under the pad to transfer the heat to the
ground plane.
TS51221
Final Datasheet
April 6, 2015
Rev 1.1
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