SH3003 Datasheet, PDF (14/30 Pages) Semtech Corporation – MicroBuddy® Support IC for Microcontrollers

SH3003
POWER MANAGEMENT
Application Information (continued)
Not authorized for release outside of Semtech - DRAFT
Clock Generator Operation (continued)
When the HF oscillator is operating alone, it can set the
frequency of the clock on the CLKOUT pin to ±0.025%,
and maintain it to ± 0.5% over temperature. This com-
pares favorable with the typical ±0.5% initial clock accu-
racy and ±0.6% overall temperature stability of ceramic
resonators. The SH3003 replaces the typical resonator,
using less space and providing better performance and
functionality.
The FLL system in the SH3003 is unconditionally stable.
To set a new frequency for the FLL, the host processor
writes the 13-bit Frequency Set value. The resulting out-
put frequency is calculated using simple formulas:
[1] and [2] (reference frequency is 32.768kHz):
FOSC = 2048 Hz * (Frequency Set value + 1) [1]
The HF oscillator can also be locked to the internal
32.768kHz signal. The absolute accuracy and stability of
the HF clock depends on the quality of the 32.768 kHz
internally generated clock; the low-frequency (LF) Oscilla-
tor System is described later in this document. When the
Real-Time Clock module of the SH3003 is used for high-
accuracy timekeeping, an external 32.768 kHz crystal
used as a reference for RTC provides excellent accuracy
and stability for the Clock Management System.
The SH3003 employs a Frequency Locked Loop (FLL) to
synchronize the HF clock to the 32.768kHz reference.
This architecture has several advantages over the com-
mon PLL (Phase Locked Loop) systems, including the
ability to stop and re-start without frequency transients or
instability, and with instant settling to a correct frequency.
The conventional PLL approach invariably includes a Low-
Pass Filter that requires a long settling time on re-start.
The primary purpose of the FLL is the maintenance of
the correct frequency while the ambient temperature is
changing. As the temperature drift of the HF oscillator is
quite small, any corrective action from the FLL system is
also small and gradual, commensurate with the tempera-
ture variation.
FOUT = FOSC / (Post-divider setting) [2]
For example, a post-divider setting of ÷8 and the Fre-
quency Set value of 4000 (0x0FA0) produce an output
frequency of 1.024MHz.
Programmable Spectrum Spreading
Most commercial electronic systems must pass regulato-
ry tests in order to determine the degree of their Electro-
magnetic Interference (EMI) affecting other electronic de-
vices. In some cases compliance with the EMI standards
is costly and complicated.
The SH3003 offers a technique for reducing the EMI. It
can be a part of the initial design strategy, or it can be
applied in the prototype stage to fix problems identified
during compliance testing. This feature of the SH3003
may greatly reduce the requirements for radiofrequency
shielding, and permits the use of simple plastic casings in
place of expensive RFI-coated or metal casings.
The SH3003 employs Programmable Spectrum Spreading
in order to reduce the RF emissions from the processor’s
clock. There are five possible settings; please see Table
2 for operating and performance figures in the 8-16MHz
range.
©2006 Semtech Corp.
14
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