SH3003 Datasheet, PDF (11/30 Pages) Semtech Corporation – MicroBuddy® Support IC for Microcontrollers

SH3003
POWER MANAGEMENT
Application Information (continued)
Low VDD Reset (continued)
On power up both the active-high and active-low reset sig-
nals are driven active. These outputs are typically valid for
a VDD level of at least 0.5V, and guaranteed to be valid for
a VDD level of 1.0V.
The reset outputs remain active until VDD rises and stays
above the level of (VBO + VHYST), where VHYST is a small
fixed amount of hysteresis, nominally 50mV, added to pre-
vent nuisance reset activations (when VDD slowly changes
near the level of VBO and some noise or power glitching is
present).
At the level of (VBO + VHYST) the power supply is consid-
ered valid. In case of the initial power-up, the reset is then
driven inactive once 6ms of valid power have elapsed. In
the case of brownout, the reset is released after a de-
lay of 6ms (but no less than 12ms from the beginning of
the brownout). Such a fast reset is possible because the
SH3003 provides a fast-starting clock that is free of crys-
tal start-up time requirements. This gives the SH3003 an
advantage over most external reset circuits, which must
have a long reset pulse duration to accommodate long
and unpredictable crystal start-up times.
The SH3003 guarantees that a valid and stable clock is
available 2ms before the reset signals are negated, so
that internal synchronous reset and initialization of the
target micro can proceed normally.
Since the clock is only active for the last 1 or 2ms of the
reset interval, when VDD has already been valid for some
time, energy savings are realized and the start-up of the
whole system is made easier. The commonly used reset
approach forces the processor to turn the oscillator on
and to run at full speed (thus consuming full power) dur-
ing the critical time when the (possibly depleted) battery is
trying to raise VDD to an acceptable level. In contrast, the
SH3003 allows the power source to charge the bypass
capacitors and raise the level of VDD with little additional
load. Only when power has stabilized is the target micro
permitted to start expending energy.
When a brownout event occurs, the SH3003 continues to
provide the clock to the target processor, but at a reduced
frequency between 500kHz and 1.0MHz. After a delay of
2ms this clock is stopped, automatically lowering the en-
ergy consumption of the whole system, (see Figure 2).
A Noise Filter (see Figure 1, Page 10) prevents reset ac-
tivations from noise and small power glitches on the VDD
line. A typical behavior is shown in Figure 3 for the VDD
level just above VBO and various amplitudes and durations
of the negative-going spikes.
When VDD is falling, both reset lines are guaranteed to
activate within 5μs from the time VBO is crossed over.
VBO + VHYST
VBO
VDD _1V
3-5 ms
RST
12 ms minimum
6 ms
NRST
CLKOUT
Undefined
1 ms
Normal
FOUT
2 ms
2 ms
Reduced FOUT
0.5-1.0 MHz
Figure 2. Operations of low VDD / Brownout Detector
10
Duration
5
Guaranteed reset
Guaranteed NO reset
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Am plitude, V
Figure 3. Response to negative voltage spikes
©2006 Semtech Corp.
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