SH3003 Datasheet, PDF (13/30 Pages) Semtech Corporation – MicroBuddy® Support IC for Microcontrollers

SH3003
POWER MANAGEMENT
Application Information (continued)
Clock Management System
The SH3003 provides a flexible tool for creating and man-
aging clocks, a versatile and accurate “any frequency”
clock synthesizer (see Figure 4). It is capable of generat-
ing any frequency in the range of 62.5kHz to 16.0MHz,
with worst-case resolution of 0.0256% (256ppm). The in-
ternal 32.768kHz clock can also be routed to the CLKOUT
pin (and HF oscillator stopped for energy savings).
onds (for a resonator), or as much as 100ms or more (for
a HF crystal), to re-start the oscillator. The SH3003 allows
the response to and service of an event to finish with a
speed previously unattainable for a simple microproces-
sor. A system with a traditional clock approach may be as
much as 100x – 10,000x slower.
The objectives, features, and behavior of the Clock Man-
agement System are aimed towards the systems that
utilize a microcontroller, a microprocessor, a DSP or an
ASIC.
The SH3003 permits the automatic sensing of the inten-
tions of the host processor, an industry first. The SH3003
shuts down its clock output when it senses that the host
processor issued a STOP instruction.
Subsequently, the SH3003 idles, consuming less than
10μA. As soon as the host exits the STOP mode, the
SH3003 instantaneously starts to supply a stable clock
(< 2μs wake-up). A typical system, constructed with a ce-
ramic resonator or a crystal as the frequency determining
element, must wait at least several hundred microsec-
Clock Generator Operation
The frequency synthesizer in the SH3003 is constructed
from the 2:1 tunable 8.0 –16.0 MHz HF oscillator followed
by a programmable “power-of-two” post-divider (see Fig-
ure 4).
The Clock Source selector and the programmable post-
scale divider allow instantaneous switching between the
32.768kHz internal clock and divided-down HF oscillator
output. There is no settling or instability when the switch
occurs. This is a preferred method for clock control in
computing systems, when the large ratio between high
and low frequency of operations allows for correspond-
ingly large and instantaneous savings in power consump-
tion.
32.768 kHz
FLL On
Frequency Locked Loop
2048 Hz
16
Logic
Clock Source
Clock On
1
Post-scaler
0
(Divide by 1, 2, 4,
8, 16, 32, 64, 128)
18-bit
DCO Code
Register
Clock Buffer
and Glue
Logic
CLKOUT
16
CLKIN
15
START/STOP
HF Digitally
Controlled
Oscillator
8-16 MHz
Force
DCO On
From / To
Serial I/O
13-bit
Frequency
Set value
8-bit Pseudo
Random Noise
Generator
Figure 4. Simplified HF Oscillator System
Spectrum
Spreading
Controls
©2006 Semtech Corp.
13
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