LC87F7CC8A Datasheet, PDF (9/21 Pages) Sanyo Semicon Device – FROM 128K byte, RAM 4096 byte on-chip 8-bit 1-chip Microcontroller

LC87F7CC8A
Port Output Types
Port form and pull-up resistor options are shown in the following table.
Port status can be read even when port is set to output mode.
Port Name
P00 to P07
Option Selected
in Units of
each bit
Option Type
1
CMOS
Output Type
Pull-up Resistor
Programmable (Note 1)
2
Nch-open drain
None
P10 to P17
each bit
1
CMOS
Programmable
2
Nch-open drain
Programmable
P70
-
None
Nch-open drain
Programmable
P71 to P73
-
None
CMOS
Programmable
P80 to P87
-
None
Nch-open drain
None
S0/PA0 to S15/PB7
-
S24/PD7 to S39/PE7
COM0/PL0 to
-
COM3/PL3
V1/PL4 to V3/PL6
-
None
None
None
CMOS
Input only
Input only
Programmable
None
None
PWM2, PWM3
-
None
CMOS
None
XT1
-
None
Input only
None
XT2
-
None
Output for 32.768kHz crystal oscillation
None
Note 1: Attachment of Port0 programmable pull-up resistors is controllable in nibble units (P00 to 03, P04 to 07).
*1: Connect as follows to reduce noise on VDD.
VSS1, VSS2, and VSS3 must be connected together and grounded.
Power
supply
LSI
VDD1
Back-up capacitors *2 _VDD2
VDD3
VSS1 VSS2 VSS3
*2: The power supply for the internal memory is VDD1 but it uses the VDD2 as the power supply for ports.
When the VDD2 is not backed up, the port level does not become “H” even if the port latch is in the “H” level.
Therefore, when the VDD2 is not backed up and the port latch is “H” level, the port level is unstable in the HOLD
mode, and the back up time becomes shorter because the through current runs from VDD to GND in the input buffer.
If VDD2 is not backed up, output “L” by the program or pull the port to “L” by the external circuit in the HOLD
mode so that the port level becomes “L” level and unnecessary current consumption is prevented.
No.A0147-9/21