LC87F7CC8A Datasheet, PDF (13/21 Pages) Sanyo Semicon Device – FROM 128K byte, RAM 4096 byte on-chip 8-bit 1-chip Microcontroller

Continued from preceding page.
Parameter
Symbol
Resistance of
Rpu
pull-up MOS Tr.
LC87F7CC8A
Pin/Remarks
Conditions
• Ports 0, 1, 7
VOH=0.9VDD
• Ports A, B, D, E
Hysterisis voltage
Pin capacitance
VHYS(1)
VHYS(2)
CP
• Ports 1, 7
• RES
Port 87 small
signal input
All pins
Input sensitivity
Vsen
Port 87 small
signal input
• All Other Terminals Connected
To VSS.
• f=1MHz
• Ta=25°C
VDD [V]
4.5 to 5.5
2.2 to 4.5
2.2 to 5.5
2.2 to 5.5
Specification
min
typ
max unit
15
35
80
kΩ
18
50
150
0.1VDD
V
0.1VDD
2.2 to 5.5
10
pF
2.2 to 5.5 0.12VDD
Vp-p
Serial I/O Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Frequency
Low level
pulse width
High level
pulse width
Frequency
Low level
pulse width
High level
pulse width
Data setup time
Data hold time
Symbol
tSCK(1)
tSCKL(1)
tSCKH(1)
tSCKHA(1)
tSCK(2)
tSCKL(2)
tSCKH(2)
tSCKHA(2)
tsDI(1)
thDI(1)
Pin/Remarks
Conditions
SCK0(P12)
See Fig. 6.
SCK0(P12)
• Continuous data
transmission/reception mode
• See Fig. 6.
• (Note 4-1-2)
• CMOS output selected
• See Fig. 6.
SB0(P11),
SI0(P11)
• Continuous data
transmission/reception mode
• CMOS output selected
• See Fig. 6.
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 6.
VDD [V]
2.2 to 5.5
min
2
1
1
4
4/3
2.2 to 5.5
tSCKH(2)
+2tCYC
2.2 to 5.5
0.03
2.2 to 5.5
0.03
Specification
typ
max
1/2
1/2
tSCKH(2)
+(10/3)
tCYC
unit
tCYC
tSCK
tCYC
Output delay
time
tdD0(1)
tdD0(2)
tdD0(3)
SO0(P10),
SB0(P11)
• Continuous data
transmission/reception mode
• (Note 4-1-3)
• Synchronous 8-bit mode
• (Note 4-1-3)
(Note 4-1-3)
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
(1/3)tCYC
+0.05
µs
1tCYC
+0.05
(1/3)tCYC
+0.15
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock
is "H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning
of output state change in open drain output mode. See Fig. 6.
No.A0147-13/21