LC7940YD Datasheet, PDF (9/11 Pages) Sanyo Semicon Device – Dot-matrix LCD Drivers

LC7940YD, LC7941YD
100 × 240–pixel LCD Panel Application
A 100 × 240–pixel LCD panel requires the following
drivers.
• 3 × LC7940YD (or LC7941YD) drivers
• 2 × LC7942YD drivers
An example using l/l00 duty cycle is shown below.
Frame signel
DI01 01
RS/LS 02
LC7942YD
#1
CP
M 063
DI064 064
DI01 01
RS/LS 02
LC7942YD
#2
CP
M ₀₃₆
DI064
O37 to O64
are open.
1,1
1,2
2,1
2,2
63,1 63,2
64,1 64,2
65,1 65,2
66,1 66,2
100,1 100,2
01
02
1,79
(m,n) : pixel address
Segment line (n)
Common line (m)
---
1,79 1,80 1,81 1,82
---
1,160 1,161
---
1,240
2,240
LCD panel (100 × 240 pixels)
---
64,80 64,81
--- _{64,160 64,161 --- 64,240}
65,80 65,81
65,160 65,161
65,240
---
---
---
--- _{100,79 100,80 100,81 100,82} --- _{100,160 100,161} --- _100,240
079 080
01
02
080
01
080
CDI
LC7940YD _{#1 CDO}
CDI ^LC7940YD #2 CDO
CDI ^LC7940YD #2 CDO
(LC7941YD)
(LC7941YD)
(LC7941YD)
1. The LC7942YD chips are cascaded by connecting
DIO64 on chip I to DIO1 on chip 2. For a 100–bit shift
register, 037 to 064 on chip 2 are left open.
2. The LC7940YD (or LC7941YD) chips are cascaded
by connecting CDO on chip I to CDI on chip 2, and
CDO on chip 2 to CDI on chip 3. CDI on chip I is tied
to GND, and CDO on chip 3 is not used. This
configuration allows the input of 240–bit serial data.
No. 6158—9/11