LV24230LS Datasheet, PDF (8/17 Pages) Sanyo Semicon Device – Compact Portable Equipment 1-Chip FM Tuner IC

LV24230LS
Digital interface specification (interface specification : reference)
(1). Characteristics of SDA and SCL bus line relative to the I²C bus interface
START Condition
Tf
SCL
Tr
TLOW
THIGH
Tf
Tr
SDA
Repeated START
THD;STA
THD;DAT TSU;DAT
TSU;STA
Parameter
SCL clock frequency
Fall time of both SDA and SCL
Rise time of both SDA and SCL
High time of SCL
Low time of SCL
Hold time of STAT condition
Hold time of Data
Set-up time of STAT condition
Set-up time of STOP condition
Set-up time of Data
Bus free time between a STOP and
Capacitivie load for each bus line
*Cb = Total capacitance of one bus line
Symbol
FSCL
Tf
Tr
THIGH
TLOW
THD _{; STA}
THD _{; DAT}
TSU _{; STA}
TSU _{; STO}
TSU _{; DAT}
TBUF
Cb
Standard-mode
min
max
0
100
300
1000
4.0
4.7
4.0
0
3.45
4.7
4.0
250
4.7
400
High_Speed-mode
unit
min
max
0
400 kHz
20+0.1Cb
300
ns
20+0.1Cb
300
ns
0.6
μs
1.3
μs
0.6
μs
0
0.9
μs
0.6
μs
0.6
μs
100
ns
1.3
μs
400 pF
(2). Register map (On Register Map)
Following is Sub address map of LV24230LS. Each register becomes 8-bit constitution.
Address
Register Name
Mode
Remark
00h
CHIP_ID
R/W
Chip ID
02h
RADIO_STAT
R
Status of Radio Station
0Bh
RFCAP
R/W
RF Cap bank
0Dh
RADIO_CTRL1
R/W
Radio Control 1
0Eh
RADIO_CTRL2
R/W
Radio Control 2
0Fh
RADIO_CTRL3
R/W
Radio Control 3
10h
TNPL
R
Tune Position Low
11h
TNPH_STAT
R
Tune Position High and Status
19h
REF_CLK_PRS
R/W
Reference clock pre-scalar
1Ah
REF_CLK_DIV
R/W
Reference clock divider
1Bh
REF_CLK_OFF
R/W
Reference clock offset
1Dh
SCN_CTRL
R/W
Scan control
1Eh
TARGET_VAL_L
R/W
Target value Low
1Fh
TARGET_VAL_H
R/W
Target value High
R : Read only register R/W : Read and Write register
No.A1989-8/17