LV24230LS Datasheet, PDF (6/17 Pages) Sanyo Semicon Device – Compact Portable Equipment 1-Chip FM Tuner IC

LV24230LS
Format of Bus Transfers
Bus transfers are primarily based on the I²C primitives
• Start condition
• Repeated start condition
• Stop condition
• Byte write
• Byte read
Start, restart, and stop conditions are specified as shown in Table 1 below.
Start
Repeated start
Stop
SCL
SDA
SCL
SDA
SCL
SDA
Fig. 1 the I²C start, repeated start and stop conditions.
For details, like timing, etc., refer to specifications of I²C.
8-bit write
8-bit data is sent from the master microcomputer to LV24230LS.
Data bit consists of MSB first and LSB last.
Data transmission is latched at the rising edge of SCL in synchronization with the SCL clock generated at the master IC.
Do not change data while SCL remains HIGH.
LV24230LS outputs the ACK bit between eighth and ninth falling edges of SCL
SCL
SDA
D7
D6
D5
D4
D3
D2
D1
D0
Ack
Fig. 2 Signal pattern of the I²C byte write
Read is of the same form as write, only except that the data direction is opposite.
Eight data bits are sent from LV24230LS to the master while Ack is sent from the master to LV24230LS.
SCL
SDA
D7
D6
D5
D4
D3
D2
D1
D0
Ack
Fig. 3 Signal pattern of the I²C byte read
The serial clock SCL is supplied from the master side. It is essential that data bit is output from LV24230LS in
synchronization with the falling edge while the master side performs latching at the rising edge.
No.A1989-6/17