LC80101M Datasheet, PDF (8/9 Pages) Sanyo Semicon Device – VICS LSI

LC80101M
Usage Notes
1. Setting the BACKUP pin low switches the LC80101M to backup mode. This is a mode in which oscillator and chip
operation are stopped to reduce current drain. This pin must be set high for normal operation. Also note that a reset
must be applied after the BACKUP pin is returned to high from low. (See Figure 4 on page 8.) The BACKUP pin
must be connected to the LC80101M V_DD pin if backup mode is not used.
2. The lines connecting this LSI to the LC72700E must be dedicated lines only used by these two chips. Do not connect
these lines to any other circuits via a bus or any other connection.
3. A reset must be applied when power is first applied. The LC72700E RST pin and this LSI’s RST2 pin can be driven
from a common signal. (See Figure 3 on page 8.)
4. The TESTON pin (pin 13) must be connected to ground.
Operation During Reset
A reset signal is applied by setting the RST2 pin input level below V_IL for at least 300 ns when the power-supply voltage
(V_DD) is 3.4 V or higher. See Figure 3.
Figure 3
All registers other than those holding data required for descrambling are reset by a reset signal. The crystal oscillator
circuit does not stop.
BACKUP Pin
A reset must be applied after the BACKUP pin is returned to high (for normal operation from low (backup mode, in
which the oscillator is stopped). See the following figure.
Figure 4
No. 5438-8/9