LC80101M Datasheet, PDF (7/9 Pages) Sanyo Semicon Device – VICS LSI

External Interface Basic Timing
LC80101M
Figure 1
Figure 1 shows how the timing changes between the LC72700E INT-R output and this LSI’s INT-R2 output. This LSI
requires the period indicated as “Note 1”, about 160 µs, following the detection of a falling edge on the INT-R signal to
set up the descrambling processing. It outputs a falling edge on INT-R2 after the note 1 time has elapsed. Serial data
reads and writes are disabled during this period.
Figure 2
Figure 2 shows the basic timing for the external interface. When this LSI is not used and the system is operated based on
the INT-R trigger, if only horizontal data is output, there will be a data readout guaranteed period of 18 – 0.068 = 17.932
ms, and if both horizontal and vertical data are read out, there will be two 9 – 0.068 = 8.932 ms data readout guaranteed
periods, one each for horizontal and vertical data output. When this LSI is used and the system is operated based on the
INT-R2 trigger, these data readout guaranteed periods are shortened by exactly the amount the INT-R2 signal is delayed,
namely 160 µs. When only horizontal data is output, the data readout guaranteed period will be 17.932 – 0.160 = 17.772
ms, and both horizontal and vertical data is output, the data readout guaranteed periods will be 8.932 – 0.160 = 8.772 ms
for both horizontal and vertical data output.
No. 5438-7/9