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LC89515K Datasheet, PDF (5/6 Pages) Sanyo Semicon Device – CD-ROM/CD-I Error Correction/ Host Interface LSI
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LC89515K
Write
RS AR No. Symbol
BIT7
0 ——
AR
0000 R0
SBOUT
msb
0001 R1
IFCTRL
CMDIEN
0010 R2
DBCL
B7
0011 R3
DBCH
0100 R4
DACL
A7
0101 R5
DACH
A15
0110 R6
DTTRG
0111 R7
1
1000 R8
1001 R9
1010 R10
DTACK
WAL
WAH
CTRL0
A7
A15
DECEN
1011 R11 CTRL1
SYIEN
1100 R12
PTL
A7
1101 R13
PTH
A15
1110 R14 CTRL2
0
1111 R15 RESET
Note: The values of the shaded bits are ignored.
BIT6
—
DTEIEN
B6
A6
A14
A6
A14
SYDEN
A6
A14
0
BIT5
—
DECIEN
B5
A5
A13
BIT4
—
CMDBK
B4
A4
A12
BIT3
A3
—
DTWAI
B3
B11
A3
A11
BIT2
A2
—
STWAI
B2
B10
A2
A10
BIT1
A1
—
DOUTEN
B1
B9
A1
A9
BIT0
A0
lsb
SOUTEN
B0
B8
A0
A8
A5
A13
E01RQ
DSCREN
A5
A13
0
A4
A12
AUTORQ
COWREN
A4
A12
BCKSL
A3
A11
ERAMRQ
MODRQ
A3
A11
DLAEN
A2
A10
WRRQ
FORMRQ
A2
A10
0
A1
A9
QRQ
MBCKRQ
A1
A9
STENCTL
A0
A8
PRQ
SHDREN
A0
A8
STENTRG
6. Additional Registers
Write
[R14] CTRL2: Control 2
STENCTL (STEN control)
0.........The external STEN pin goes to 0 when the microprocessor writes one byte of status information. (This is
identical to LC8951 operation.)
1.........The external STEN pin goes to 0 due to 0 being written to the STENTRG register when the
microprocessor writes * bytes of status information.
This bit is set to 0 on reset.
STENTRG (STEN trigger)
This bit is only valid when STENCTL is 1.
The external STEN pin goes to 0 when a 0 is written to this bit.
This bit is reset when the host reads the last byte, i.e., when the external STEN pin has become 1.
DLAEN (drive last address enable)
When WRRQ is set to 0 during buffering, buffering continues until the next SYNC signal arrives and then stops.
This results in the sectors that are buffered when WRRQ was set to 0 becoming valid. (This bit is set to 0 on
reset.)
BCKSL (bit clock select)
Setting this bit to 1 allows the bit clock from the CD-DSP to be inverted. (SDATA is acquired on the rising edge
of BCK.) (This bit is set to 0 on reset.)
No. 4272-5/6
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