LC89515K Datasheet, PDF(4/6 Page) Sanyo Semicon Device – CD-ROM/CD-I Error Correction/ Host Interface LSI

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

LC89515K Datasheet, PDF (4/6 Pages) Sanyo Semicon Device – CD-ROM/CD-I Error Correction/ Host Interface LSI

◁

LC89515K

Furthermore, the LC89515K SELDRQ pin can be used to perform DRQ (data request) transfers. This is a technique

in which transfers are performed by the host outputting HRD pulses according to a data request signal output from

the LC89515K and is similar to DMA controller operation.

When the last byte of the count specified by the control microprocessor is read, EOP goes active while the read pulse

is output. Also DTEN is set inactive after this time. Next, a transfer complete interrupt is issued to inform the control

microprocessor that the transfer to the host has completed.

The LC89515K control microprocessor can pass the decoding result for the data requested by the host and the CD-

ROM drive status information to the host by writing to the LC89515K internal status registers. The status registers

are a 12-byte FIFO, and the host reads out data while the STEN signal is low. The STEN signal goes high when the

last byte is read. The LC89515K has nothing to do with the content of the status registers.

Since the command and status registers are neither interpreted nor executed by the LC89515K, the LC89515K user

can define the command and status data as unrestricted protocols between the host and the microprocessor. This

allows CD-ROM application systems to be designed without restriction, and also allows an existing system to be

replaced by a system using the LC89515K.

4. Points Common to All Blocks

The LC89515K performs data input and decoding at the same time in a pipelined manner. Also, writes of input data

to the buffer RAM, writes of data to be decoded, and reads to the buffer RAM for transfers to the host all proceed at

the same time with synchronization always being maintained by the LC89515K. Therefore there is no need for the

control microprocessor to be concerned with which master (system block) is accessing the buffer RAM.

5. Register Table

Read

RS AR No.

0 ââ

0000 R0

0001 R1

0010 R2

0011 R3

0100 R4

0101 R5

0110 R6

0111 R7

1000 R8

1001 R9

1010 R10

1011 R11

1100 R12

1101 R13

1110 R14

1111 R15

Symbol

COMIN

IFSTAT

DBCL

DBCH

HEAD0

HEAD1

HEAD2

HEAD3

PTL

PTH

WAL

WAH

STAT0

STAT1

STAT2

STAT3

BIT7

msb

CMDI

DTEI

msb

A15

CRCOK

MINERA

RMOD3

VALST

Note: The values of the shaded bits are ignored.

BIT6

DTEI

A14

ILSYNC

SECERA

RMOD2

WLONG

BIT5

DECI

DTEI

A13

NOSYNC

BLKERA

RMOD1

CBLK

BIT4

DTEI

A12

LBLK

MODERA

RMOD0

BIT3

DTBSY

B11

A11

WSHORT

SH0ERA

MODE

BIT2

STBSY

B10

A10

SBLK

SH1ERA

NOCOR

BIT1

DTEN

ERABLK

SH2ERA

RFORM1

BIT0

lsb

STEN

lsb

UCEBLK

SH3ERA

RFORM0

No. 4272-4/6

▷