LC75890W Datasheet, PDF (5/32 Pages) Sanyo Semicon Device – 1/4duty and Static Drive General-Purpose LCD Display Drivers

LC75890W, LC75890E
1. When CL is stopped at the low level
CE
CL
tf
DI
tφL
tr
tds
tφH
VIH1
50%
VIL1
VIH1
VIL1
tdh
VIH1
tcp tcs
[Figure 1]
VIL1
tch
2. When CL is stopped at the high level
CE
tφL
tφH
CL
tf
tr
DI
tds
tdh
VIH1
VIH1
50%
VIL1
VIH1
VIL1
tcp tcs
[Figure 2]
VIL1
tch
3. OSCI pin clock timing in external clock operating mode
OSCI
tCKH
tCKL
VIH2
50%
VIL2
[Figure 3]
1
fCK= _{tCKH + tCKL} [kHz]
DCK=
tCKH
tCKH + tCKL
× 100[%]
No.A1971-5/32