LC75890W Datasheet, PDF (17/32 Pages) Sanyo Semicon Device – 1/4duty and Static Drive General-Purpose LCD Display Drivers

LC75890W, LC75890E
Control Data Functions
(1) BD1 to BD37 … Display blinking control data of each segment output pin
These control data bits are used to set the display segment blinking corresponding to each segment output pin.
BDn
Display segment blinking states of segment output pin Sn
0
The display segments are not blinked.
The display segments corresponding to the segment output pin Sn that the contents of display
1
data are "1" are blinked.
Note: The BDn (n=1 to 37) are the control data setting the blinking state of the display segments for segment output
pins Sn (n=1 to 37). However, in the case of the LC75890E(QIP44M), the control data are effective for only
BD1 to BD11, BD13 to BD23, BD25 to BD34, and BD37.
For example, the display state of segment output pin S21 becomes as follows when the contents of display data are
(D81, D82, D83, D84)=(1, 0, 1, 0) in 1/4 duty drive
BD21
D81
Display data
D82
D83
Display states of segment output pin S21
D84
COM1
COM2
COM3
COM4
0
1
0
1
0
on
off
on
off
1
1
0
1
0
blink
off
blink
off
(2) BF0 to BF2 … Segment blinking frequency setting control data
These control data bits are used to set the display segment blinking frequency
Control data
Segment blinking frequency fb[Hz]
BF0 BF1 BF2
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
Internal oscillator operating mode
(The control data OC is 0,
fosc=300[kHz]typ)
fosc/600000
fosc/360000
fosc/300000
fosc/240000
fosc/180000
fosc/150000
fosc/120000
External clock operating mode
(The control data OC is 1
and EXF is 0, fCK1=300[kHz]typ)
fCK1/600000
fCK1/360000
fCK1/300000
fCK1/240000
fCK1/180000
fCK1/150000
fCK1/120000
1
1
1
fosc/100000
fCK1/100000
External clock operating mode
(The control data OC is 1
and EXF is 1, fCK2=38[kHz]typ)
fCK2/75000
fCK2/45000
fCK2/37500
fCK2/30000
fCK2/22500
fCK2/18750
fCK2/15000
fCK2/12500
(3) FC0 to FC2 … Common/segment output waveform frame frequency setting control data
These control data bits set the frame frequency of the common and segment output waveforms.
Control data
Common/segment output waveform frame frequency fo[Hz]
Internal oscillator operating mode
External clock operating mode
External clock operating mode
FC0 FC1 FC2
(The control data OC is 0,
(The control data OC is 1
(The control data OC is 1
fosc=300[kHz]typ)
and EXF is 0, fCK1=300[kHz]typ)
and EXF is 1, fCK2=38[kHz]typ)
0
0
0
fosc/4608
fCK1/4608
fCK2/576
0
0
1
fosc/3456
fCK1/3456
fCK2/432
0
1
0
fosc/3072
fCK1/3072
fCK2/384
0
1
1
fosc/2304
fCK1/2304
fCK2/288
1
0
0
fosc/1536
fCK1/1536
fCK2/192
1
0
1
fosc/1152
fCK1/1152
fCK2/144
1
1
0
fosc/768
fCK1/768
fCK2/96
Note: When is setting (FC0, FC1, FC2)=(1, 1, 1), the frame frequency is same as frame frequency at the time of the
(FC0, FC1, FC2)=(0, 1, 0) setting (fosc/3072, fCK1/3072, fCK2/384).
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