LC75897PW Datasheet, PDF (4/34 Pages) Sanyo Semicon Device – 1/3, 1/4-Duty General-Purpose LCD Display Driver

1. When CL is stopped at the low level
CE
tφH
tφL
VIH1
CL 50%
VIL1
tr
tf
VIH1
DI
VIL1
tds
tdh
LC75897PW
VIH1
tcp tcs
Figure 2
2. When CL is stopped at the high level
VIH1
CE
tφL
tφH
VIH1
CL
50%
VIL1
tf
tr
tcp tcs
DI
VIH1
VIL1
tds
tdh
Figure 3
3. OSC pin clock timing in external clock operating mode
OSC
VIH2
50%
VIL2
tCKH
tCKL
1
fCK = _tCKH+tCKL [kHz]
DCK =
tCKH
tCKH+ tCKL
×100[%]
Figure 4
VIL1
tch
VIL1
tch
No.A0549-4/34