LC75897PW Datasheet, PDF (17/34 Pages) Sanyo Semicon Device – 1/3, 1/4-Duty General-Purpose LCD Display Driver

LC75897PW
(3) PS10, PS11, PS20, PS21, PS30, PS31, PS40, PS41, PS5 to PS8: Segment output port/general-purpose output
port/PWM output port/clock output port switching control data
This control data is used to set the state of output pins S1/P1 to S8/P8.
PS10 and PS11: Output pin (S1/P1) state settings
PS10
PS11
Output pin (S1/P1) state
0
0
Segment output port (S1)
1
0
General-purpose output port (P1)
0
1
PWM output port (P1)
PS20 and PS21: Output pin (S2/P2) state settings
PS20
PS21
Output pin (S2/P2) state
0
0
Segment output port (S2)
1
0
General-purpose output port (P2)
0
1
PWM output port (P2)
PS30 and PS31: Output pin (S3/P3) state settings
PS30
PS31
Output pin (S3/P3) state
0
0
Segment output port (S3)
1
0
General-purpose output port (P3)
0
1
PWM output port (P3)
PS5: Output pin (S5/P5) state settings
PS5
Output pin (S5/P5) state
0
Segment output port (S5)
1
General-purpose output port (P5)
PS40 and PS41: Output pin (S4/P4) state settings
PS40
PS41
Output pin (S4/P4) state
0
0
Segment output port (S4)
1
0
General-purpose output port (P4)
Clock output port (P4)
0
1
(clock frequency fosc/2, fCK/2)
Clock output port (P4)
1
1
(clock frequency fosc/8, fCK/8)
PS6: Output pin (S6/P6) state settings
PS6
Output pin (S6/P6) state
0
Segment output port (S6)
1
General-purpose output port (P6)
PS7: Output pin (S7/P7) state settings
PS8: Output pin (S8/P8) state settings
PS7
Output pin (S7/P7) state
PS8
Output pin (S8/P8) state
0
Segment output port (S7)
0
Segment output port (S8)
1
General-purpose output port (P7)
1
General-purpose output port (P8)
For example, if PS10 and PS11 are set to 0 and 1 respectively, PS20 and PS21 to 0 and 1 respectively, PS30 and PS31
to 0 and 1 respectively, PS40 and PS41 to 1 and 0 respectively, PS5 to 1, PS6 to 1, PS7 to 0, and PS8 to 0, the output
pins S1/P1 to S3/P3 are selected as PWM output ports, the output pins S4/P4 to S6/P6 as general-purpose output ports,
and the output pins S7/P7 and S8/P8 as segment output ports.
(4) CT0 to CT2: Display contrast setting control data
This control data is used to set the display contrast.
CT0 to CT2: Display contrast settings (7 steps)
CT0
CT1
CT2
Level of LCD drive bias 3/3 voltage power supply VLCD0
0
0
0
1.00VLCD = VLCD- (0.05VLCD×0)
1
0
0
0.95VLCD = VLCD- (0.05VLCD×1)
0
1
0
0.90VLCD = VLCD- (0.05VLCD×2)
1
1
0
0.85VLCD = VLCD- (0.05VLCD×3)
0
0
1
0.80VLCD = VLCD- (0.05VLCD×4)
1
0
1
0.75VLCD = VLCD- (0.05VLCD×5)
0
1
1
0.70VLCD = VLCD- (0.05VLCD×6)
Note that although the contrast of the display can be adjusted by running the internal display contrast adjustment circuit,
it is also possible to adjust it by changing the voltage level on the LCD driver block power supply VLCD pin. However,
VLCD0 must always be greater than or equal to 2.7V.
(5) DR: 1/2 bias drive or 1/3 bias drive switching control data
This control data bit selects either 1/2 bias drive or 1/3 bias drive.
DR
Bias drive scheme
0
1/3 bias drive
1
1/2 bias drive
No.A0549-17/34