LC87F2J32A Datasheet, PDF (3/30 Pages) Sanyo Semicon Device – 8-bit 1-chip Microcontroller

LC87F2J32A
„AD Converter: 12 bits/8 bits × 14 channels
• 12/8 bits AD converter resolution selectable
„PWM: Multifrequency 12-bit PWM × 2 channels
„Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
1) _{Noise rejection function}
(Units of noise rejection filter : about 120μs, when selecting a 32.768kHz crystal oscillator as a clock.)
2) Supporting reception formats with a guide-pulse of halt-clock/clock/none.
3) Determines a end of reception by detecting a no-signal periods (No carrier).
(Supports same reception format with a different bit length.)
4) X’tal HOLD mode release function
„Clock Output Function
• Can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as
the system clock.
• Can generate the source clock for the subclock.
„Watchdog timer
• External RC watchdog timer
• Interrupt and reset signals selectable
„Interrupts
• 24 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4/REMOREC2
4
0001BH
H or L
INT3/INT5/ BT0/BT1
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0/UART1 receive
8
0003BH
H or L
SIO1/UART1 transmit
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0/T4/T5/PWM0, PWM1
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• IFLG ^{(List of interrupt source flag function)}
1) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the table
above).
„Subroutine Stack Levels: 512 levels (the stack is allocated in RAM)
„High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits (12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits (12 tCYC execution time)
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