LV23401V_11 Datasheet, PDF (23/24 Pages) Sanyo Semicon Device – For Home Stereo System 1-chip Tuner IC Incorporating PLL

Serial data timing
LV23401V
CE
CL
VIH
VIL
VIH
DI
VIL
tSU
DO
Internal
data latch
tCH
tCL
VIH
tHD ^VIL
VIH
VIL
tEL
VIH
tES
VIL
VIH
VIL
tEH
tDC
tDC
tDH
<< When CL stops at the “L” level >>
tLC
OLD NEW
CE
CL
DI
DO
Internal
data latch
tCL
VIH
VIL
VIH
VIL
tSU
tCH
VIH
VIH
VIH
tEL
VIL
tES
tHD ^VIL
tDC
<< When CL stops at the “H” level >>
VIL
tEH
tDH
tLC
OLD NEW
Parameter
Data setup time
Data hold time
Clock “L” level time
Clock “H” level time
CE wait time
CE setup time
CE hold time
Data latch change time
Data output time
Symbol
tSU
tHD
tCL
tCH
tEL
tES
tEH
tLC
tDC
tDH
Pin
DI, CL
DI, CL
CL
CL
CE, CL
CE, CL
CE, CL
DO, CL
DO, CE
Conditions
Differs depending on the pull-up resistance
and substrate capacity
Min
Typ
0.75
0.75
0.75
0.75
0.75
0.75
0.75
Max
Unit
μs
μs
μs
μs
μs
μs
μs
0.75
μs
0.35
μs
No.A1746-23/24