LV23401V_11 Datasheet, PDF (15/24 Pages) Sanyo Semicon Device – For Home Stereo System 1-chip Tuner IC Incorporating PLL

LV23401V
Register 0Fh – AMCTRL – AM Station Control (Read/Write)
7
AMDIV[2:0]
Bit 7 – 5 :
Bit 7 :
Bit 6 :
Bit 5 :
6
5
AMDIV[2:0] : AM Clock Divider
AM_CD2 : AM Clock Divider bit 2.
AM_CD1 : AM Clock Divider bit 1.
AM_CD0 : AM Clock Divider bit 0.
4
AM_CAL
3
ACAP11
2
ACAP10
1
ACAP9
0
ACAP8
Note : AMCD[2:0] uses the frequency of FM belt even for the AM belt to lower.
Set the machine of the AM dividing frequency to turning off at FM mode.
AM_CD[2:0] Rate of dividing frequency
Rough estimate AM-RF frequency (In kHz)
0,1
Divider OFF
0 (FM mode)
2
224
338 – 483
3
160
474 – 676
4
112
676 – 966
5
80
947 – 1353
6
64
1183 – 1692
7
48
1578 - 2256
Bit 4 :
Bit 3 – 0 :
Bit 3 :
Bit 2 :
Bit 1 :
Bit 0 :
NA ( 0 Fixation)
AMCAP[11:8] : AM antenna capacitor bank.
AMCAP_bit11
AMCAP_bit10
AMCAP_bit9
AMCAP_bit8
Register 10h – DO_REF_CLK_CNF – Do output mode and reference clock configuration (Read/Write)
7
6
5
4
3
2
1
0
IPOL
DO_SEL[1:0]
EXT_CLK_CFG[1:0]
FS_S[2:0]
Bit 7 :
IPOL : Indicator (DO pin _SD/ST mode) polarity
0 = SD/ST Active Low (The same state change as 13pin – SD pin / 14pin – ST pin )
1 = SD/ST Active High (State change opposite to 13pin – SD pin / 14pin – ST pin )
Note : This bit doesn't influence the polarity of the serial data.
Bit 6 -5 :
DO_SEL : DO pin select (DO pin output mode select)
DO_SEL[1:0]
DO pin
00
Serial data output mode
01
ST pin mode
10
SD pin mode
11
Local position confirmation mode
DO pin is used by observing the position (Upper heterodyne / Lower heterodyne) of a state of SD pin/ST pin besides the serial data output and local
OSC.
* The state of DO pin changes synchronizing with SD pin / ST pin when DO_SEL is set to (01b) or (10b).
* The state of DO pin changes by the position of Local OSC when DO is set to (11b). Lower heterodyne = 0, Upper heterodyne = 1
* Set DO_SEL to (00b) when you output the serial data.
Bit 4 – 3 :
EXT_CLK_CFG[1:0] : External clock setting
EXT_CLK_CFG[1:0]
00
01
10
11
Reference clock
Off
The external clock is supplied.
32768Hz Crystal oscillation
Unused
Bit 2 – 0 :
FS_S[2:0] : SD(Station Detector) operate level setting (distinguishes at the FS level )
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