LC88F52H0A Datasheet, PDF (20/31 Pages) Sanyo Semicon Device – FROM 128K byte, RAM 6K byte on-chip 16-bit 1-chip Microcontroller

Continued from preceding page
Parameter
Symbol
Stop condition
setup time
tSU;STO
LC88F58B0A
Applicable
Pin/Remarks
SM0CK(P22)
SM0DA(P23)
Conditions
• See Fig. 8.
VDD[V]
min
Specification
typ
max
unit
1.0
Tfilt
Data hold time
tSU;STOx
SM0CK(P22)
SM0DA(P23)
• Standard clock mode
• Specified as interval up to time
2.2 to 5.5
4.9
when output state starts changing.
• High-speed clock mode
• Specified as interval up to time
1.1
when output state starts changing.
tHD;DAT
SM0CK(P22) • See Fig. 8.
SM0DA(P23)
0
tHD;DATx SM0CK(P22) • Specified as interval up to time
2.2 to 5.5
SM0DA(P23)
when output state starts changing.
1
μs
Tfilt
1.5
Data setup time
tSU;DAT
SM0CK(P22) • See Fig. 8.
SM0DA(P23)
1
2.2 to 5.5
Tfilt
tSU;DATx SM0CK(P22) • Specified as interval up to time
SM0DA(P23)
when output state starts changing.
1tSCL
-1.5Tfilt
SM0CK and
tF
SM0CK(P22) • See Fig. 8.
SM0DA pins fall
time
SM0DA(P23)
2.2 to 5.5
300
tF
SM0CK (P22) • When SMIIC register control bits,
20
5
SM0DA (P23) PSLW=1, P5V=1
+0.1Cb
250
ns
• When SMIIC register control bits,
20
3
250
PSLW=1, P5V=0
+0.1Cb
• SM0CK, SM0DA port output
FAST mode
3 to 5.5
100
• Cb≤400pF
Note 4-6-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-6-2: The value of Tfilt is determined by the values of the register SMIC0BRG, bits 7 and 6 (BRP1, BRP0) and
the system clock frequency.
BRP1
BRP0
Tfilt
0
0
tCYC×1
0
1
tCYC×2
1
0
tCYC×3
1
1
tCYC×4
Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range:
250ns ≥ Tfilt >140ns
Note 4-6-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 400pF
Note 4-6-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows:
250ns ≥ Tfilt >140ns
BRDQ (bit5) = 1
SCL frequency setting ≤ 100kHz
The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows:
250ns ≥ Tfilt >140ns
BRDQ (bit5) = 0
SCL frequency setting ≤ 400kHz
No.A1951-20/31