LC75884E Datasheet, PDF (19/27 Pages) Sanyo Semicon Device – 1/4 Duty LCD Display Drivers with Key Input Function

LC75884E, LC75884W
Note: t1 ≥ 1 [ms] (Logic block power supply voltage V_DD rise time)
t2 ≥ 0
t3 ≥ 0
t4 ≥ 1 [ms] (Logic block power supply voltage V_DD fall time)
(2) Reset when the logic block power supply voltage is in the allowable operating range (V_DD = 4.5 to 6.0V)
The system is reset when the RES pin is set low, and the reset is cleared by setting RES pin high.
2. LC75884E/W internal block states during the reset period
• CLOCK GENERATOR
Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined
after the S0 and S1 control data bits are transferred.
• COMMON DRIVER, SEGMENT DRIVER & LATCH
Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
• KEY SCAN
Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.
• KEY BUFFER
Reset is applied and all the key data is set to low.
• CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER
Since serial data transfer is possible, these circuits are not reset.
No. 6086-19/27