LC75884E Datasheet, PDF (18/27 Pages) Sanyo Semicon Device – 1/4 Duty LCD Display Drivers with Key Input Function

LC75884E, LC75884W
Voltage Detection Type Reset Circuit (VDET)
This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage
drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET,
which is 3.0V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power
supply line so that the logic block power supply voltage V_DD rise time when the logic block power is first applied and the
logic block power supply voltage V_DD fall time when the voltage drops are both at least 1 ms. (See Figure 3.)
Power Supply Sequence
The following sequences must be observed when power is turned on and off. (See Figure 3.)
• Power on :Logic block power supply(V_DD) on → LCD driver block power supply(V_LCD) on
• Power off:LCD driver block power supply(V_LCD) off → Logic block power supply(V_DD) off
However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off
at the same time.
System Reset
The LC75884E/W supports the reset methods described below. When a system reset is applied, display is turned off, key
scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning
become possible.
1. Reset methods
(1) Reset at power-on and power-down
If at least 1 ms is assured as the logic block supply voltage V_DD rise time when logic block power is applied, a system
reset will be applied by the VDET output signal when the logic block supply voltage is brought up. If at least 1 ms is
assured as the logic block supply voltage V_DD fall time when logic block power drops, a system reset will be applied in
the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is cleared at the
point when all the serial data (the display data D1 to D220 and the control data) has been transferred, i.e., on the fall of
the CE signal on the transfer of the last direction data, after all the direction data has been transferred. However, the
above operations will be performed regardless of the state (high or low) of the RES pin. If RES is high, the reset will be
cleared at the point the above operations are completed. On the other hand, if RES is low, the system will remain in the
reset period as long as RES is not set high, even if the above operations are completed. (See Figure 3.)
No. 6086-18/27