LV4141W Datasheet, PDF (18/27 Pages) Sanyo Semicon Device – Bi-CMOS LSI For LCD Panel Drive Single Chip IC

(2) 3-wave serial format
LV4141W
DATA
SCLK
LOAD
Data length : 16bit
Clock frequency : 3MHz or less
DATA loaded at start of "LOAD" only when 16-clock of "SCLK" is entered in the "LOAD" "L" period.
(Note) Data not loaded in case of 15 or less clocks or 17 or more clocks in "LOAD" "L" period
(3) Data output timing
1. Various mode settings
Some items (with a circle in the V latch column of data specification) have data set at fall of the vertical
synchronous signal and some (without a mark in the V latch column) do not.
When data immediately before the vertical synchronous signal is transferred for multiple times, data immediately
before vertical synchronous signal becomes effective for items to be set with the vertical synchronous signal. For
items for whcih no setting is made, data becomes effective each time "DATA" is loaded.
2. Setting of the electric volume
D/A output data is changed at the same time with loading of "DATA."
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