LC87F1JJ8B Datasheet, PDF (18/28 Pages) Sanyo Semicon Device – 8-bit 1-chip Microcontroller with USB-host controller

LC87F1JJ8B
3. SIO4 Serial I/O Characteristics (Note 4-3-1)
Parameter
Frequency
Symbol
tSCK(5)
Pin/
Remarks
SCK4(P24)
Conditions
See Fig. 9.
Specification
VDD[V]
min
typ
max
unit
2
Low level
tSCKL(5)
1
pulse width
High level
tSCKH(5)
1
pulse width
tSCKHA(5a)
• USB, SIO0 continuous transfer
mode, AIF, SIO9, and DMCOPY
not used at the same time.
4
• See Fig. 9.
• (Note 4-3-2)
tSCKHA(5b)
• USB used at the same time
2.7 to 5.5
• SIO0 continuous transfer mode,
tCYC
AIF, SIO9, and DMCOPY not
7
used at the same time.
• See Fig. 9.
• (Note 4-3-2)
tSCKHA(5c)
• USB, SIO0 continuous transfer
mode, SIO9, and DMCOPY used
at the same time.
12
• AIF not used at the same time.
• See Fig. 9.
• (Note 4-3-2)
Frequency
tSCK(6)
SCK4(P24) • When CMOS output type is
4/3
selected.
Low level
pulse width
High level
pulse width
tSCKL(6)
tSCKH(6)
• See Fig. 9.
1/2
tSCK
1/2
(Note 4-3-3)
tSCKHA(6a)
• USB, SIO0 continuous transfer
mode, AIF, SIO9, and DMCOPY
not used at the same time.
• When CMOS output type is
selected.
tSCKH(6)
+
(5/3)tCYC
tSCKH(6)
+
(10/3)tCYC
• See Fig. 9.
tSCKHA(6b)
• USB used at the same time.
• SIO0 continuous transfer mode,
2.7 to 5.5
AIF, SIO9, and DMCOPY not
tSCKH(6)
tSCKH(6)
used at the same time.
• When CMOS output type is
+
(5/3)tCYC
+
(19/3)tCYC
tCYC
selected.
• See Fig. 9.
tSCKHA(6c)
• USB, SIO0 continuous transfer
mode, SIO9, and DMCOPY used
at the same time.
tSCKH(6)
tSCKH(6)
• AIF not used at the same time.
+
+
• When CMOS output type is
(5/3)tCYC
(34/3)tCYC
selected.
• See Fig. 9.
Note 4-3-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
Note 4-3-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the period
from the time SI4RUN is set with the serial clock set high to the falling edge of the first serial clock must
be longer than tSCKHA.
Note 4-3-3: When using the serial clock output, make sure that the load at the SCK4 (P24) pin meets the following
conditions:
Clock rise time tSCKR < 0.037μs (see Figure 12.) at Ta=+25°C, VDD=3.3V
Continued on next page.
No.A1538-18/28